Patents by Inventor Shunji Imanaga
Shunji Imanaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7696530Abstract: A sensor includes a first gate electrode, a second gate electrode, a semiconductor layer, a gate-insulating layer, a source electrode, a drain electrode, and a sensing portion including an accommodating part and a receiving layer. The first and second gate electrodes are opposed to each other with the sensing portion, the semiconductor layer, and the gate-insulating layer therebetween. One surface of the semiconductor layer is in contact with a surface of the sensing portion, and another surface of the semiconductor layer is in contact with the gate-insulating layer. A surface of the gate-insulating layer is in contact with the second gate electrode. The first gate electrode and the receiving layer are opposed to each other with the accommodating part therebetween. The source and drain electrodes are in contact with the semiconductor layer.Type: GrantFiled: June 8, 2007Date of Patent: April 13, 2010Assignee: Canon Kabushiki KaishaInventors: Tetsushi Yamamoto, Tadahiko Hirai, Shunji Imanaga
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Publication number: 20070295988Abstract: A sensor includes a first gate electrode, a second gate electrode, a semiconductor layer, a gate-insulating layer, a source electrode, a drain electrode, and a sensing portion including an accommodating part and a receiving layer. The first and second gate electrodes are opposed to each other with the sensing portion, the semiconductor layer, and the gate-insulating layer therebetween. One surface of the semiconductor layer is in contact with a surface of the sensing portion, and another surface of the semiconductor layer is in contact with the gate-insulating layer. A surface of the gate-insulating layer is in contact with the second gate electrode. The first gate electrode and the receiving layer are opposed to each other with the accommodating part therebetween. The source and drain electrodes are in contact with the semiconductor layer.Type: ApplicationFiled: June 8, 2007Publication date: December 27, 2007Applicant: CANON KABUSHIKI KAISHAInventors: Tetsushi YAMAMOTO, Tadahiko HIRAI, Shunji IMANAGA
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Patent number: 6140169Abstract: A GaN-type field effect transistor exhibits a large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially laminated on a substrate with a buffer layer therebetween. A gate electrode is formed on the gate insulating film. A source electrode and a drain electrode are disposed at the both sides of the gate electrode and are electrically connected to the channel layer via openings. The channel layer is formed from n-type GaN. The gate insulating film is made from AlN, which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving a large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a Si-MOS-type FET, resulting in the formation of an inversion layer.Type: GrantFiled: April 1, 1999Date of Patent: October 31, 2000Assignee: Sony CorporationInventors: Hiroji Kawai, Shunji Imanaga
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Patent number: 6064082Abstract: A heterojunction field effect transistor realizing a high performance by a significant decrease. in source resistance while maintaining a sufficiently high gate resistivity to voltage is provided. Sequentially stacked on a c-face sapphire substrate via a buffer layer are an undoped GaN layer, undoped Al.sub.0.3 Ga.sub.07 N layer, undoped GaN channel layer, undoped Al.sub.0.15 Ga.sub.0.85 N spacer layer, n-type Al.sub.0.15 Ga.sub.0.85 N electron supply layer, graded undoped Al.sub.z Ga.sub.1-z N barrier layer and n-type Al.sub.0.06 Ga.sub.0.94 N contact layer, and a gate electrode, source electrode and drain electrode are formed on the n-type Al.sub.0.06 Ga.sub.0.94 N contact layer to form a AlGaN/GaN HEMT. The Al composition z in the graded undoped Al.sub.z Ga.sub.1-z N barrier layer continuously decreases from 0.15 to 0.06, for example, from the n-type Al.sub.0.15 Ga.sub.0.85 N electron supply layer toward the n-type Al.sub.0.06 Ga.sub.0.94 N contact layer. An n.sup.Type: GrantFiled: May 29, 1998Date of Patent: May 16, 2000Assignee: Sony CorporationInventors: Hiroji Kawai, Shunji Imanaga, Toshimasa Kobayashi
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Patent number: 5929467Abstract: A GaN-type field effect transistor exhibits a large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially laminated on a substrate with a buffer layer therebetween. A gate electrode is formed on the gate insulating film. A source electrode and a drain electrode are disposed at the both sides of the gate electrode and are electrically connected to the channel layer via openings. The channel layer is formed from n-type GaN. The gate insulating film is made from AlN, which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving a large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a Si-MOS-type FET, resulting in the formation of an inversion layer.Type: GrantFiled: December 3, 1997Date of Patent: July 27, 1999Assignee: Sony CorporationInventors: Hiroji Kawai, Shunji Imanaga
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Patent number: 5506855Abstract: A semiconductor laser using II-VI compound semiconductors and capable of emitting blue to ultraviolet light is disclosed. The semiconductor laser is configured to sandwich an active layer made of a Zn.sub.x Mg.sub.1-x S.sub.y Se.sub.1-y compound semiconductor where 0.ltoreq.x<1 and 0.ltoreq.y.ltoreq.1 excluding ranges of 1.2y-2.2x.gtoreq.1, 1.3y-3.9x.gtoreq.1, x.gtoreq.0, and y.ltoreq.1 by an n-type cladding layer and a p-type cladding layer from opposite sides.Type: GrantFiled: November 9, 1994Date of Patent: April 9, 1996Assignee: Sony CorporationInventors: Akira Ishibashi, Shoji Kanamaru, Hiroyuki Okuyama, Shunji Imanaga
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Patent number: 4758870Abstract: A III-V semiconductor device is disclosed, which includes an emitter region, an emitter barrier region having such a barrier height as to substantially restrict a thermionic emission current as compared with a tunneling current and such a barrier width as to permit the tunneling current, a base region containing indium and having higher electron affinity than said emitter region and a collector barrier region having such a barrier height as to substantially prohibit a thermally distributed electron from overflowing and such a barrier width as to substantially prohibit the tunneling current.Type: GrantFiled: March 19, 1985Date of Patent: July 19, 1988Assignee: Director-General of the Agency of Industrial Science & Technology Itaru TodorikiInventors: Ichiro Hase, Hiroji Kawai, Shunji Imanaga, Kunio Kaneko