Patents by Inventor Shunji Kuwahara
Shunji Kuwahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11705432Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.Type: GrantFiled: July 1, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
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Publication number: 20210327856Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.Type: ApplicationFiled: July 1, 2021Publication date: October 21, 2021Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
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Patent number: 11081468Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.Type: GrantFiled: August 28, 2019Date of Patent: August 3, 2021Assignee: Micron Technology, Inc.Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
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Publication number: 20210066247Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.Type: ApplicationFiled: August 28, 2019Publication date: March 4, 2021Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
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Patent number: 9041436Abstract: To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.Type: GrantFiled: October 26, 2011Date of Patent: May 26, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Shunji Kuwahara, Hiroki Fujisawa
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Patent number: 8461867Abstract: To include an output terminal, unit buffers, and plural output-wiring paths that respectively connect the unit buffers and the output terminal. The output wiring paths have individual output wiring sections individually allocated to corresponding unit buffers. Unit buffers corresponding to these output wiring paths are common output wiring sections shared by the output wiring paths, and are connected to the output terminal without via a common output wiring section having a higher resistance value than those of the individual output wiring sections. Accordingly, an deviation of impedance due to a parasitic resistance between the output terminal and the unit buffers is suppressed.Type: GrantFiled: September 10, 2010Date of Patent: June 11, 2013Assignee: Elpida Memory, Inc.Inventors: Shunji Kuwahara, Hiroki Fujisawa
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Patent number: 8278973Abstract: To include two counter circuits that change impedances of two replica circuits, respectively, and an impedance adjustment control circuit that controls the counter circuits to update count values of the counter circuits. The impedance adjustment control circuit controls one of the counter circuits to finish updating the count value of the counter circuit in response to a change of the impedance of the corresponding replica circuit from a state of being lower than an impedance of an external resistor to a state of being higher than the impedance of the external resistor, and controls the other counter circuit to finish updating the count value of the other counter circuit in response to a change of the impedance of the other replica circuit from a state of being higher than the impedance of the former replica circuit to a state of being lower than the impedance of the former replica circuit. With this configuration, the adjust errors generated in the replica circuits are canceled.Type: GrantFiled: February 17, 2010Date of Patent: October 2, 2012Assignee: Elpida Memory, Inc.Inventors: Shunji Kuwahara, Hiroki Fujisawa
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Publication number: 20120119578Abstract: To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.Type: ApplicationFiled: October 26, 2011Publication date: May 17, 2012Applicant: Elpida Memory, Inc.Inventors: Shunji Kuwahara, Hiroki Fujisawa
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Publication number: 20110062984Abstract: To include an output terminal, unit buffers, and plural output-wiring paths that respectively connect the unit buffers and the output terminal. The output wiring paths have individual output wiring sections individually allocated to corresponding unit buffers. Unit buffers corresponding to these output wiring paths are common output wiring sections shared by the output wiring paths, and are connected to the output terminal without via a common output wiring section having a higher resistance value than those of the individual output wiring sections. Accordingly, an deviation of impedance due to a parasitic resistance between the output terminal and the unit buffers is suppressed.Type: ApplicationFiled: September 10, 2010Publication date: March 17, 2011Applicant: Elpida Memory, Inc.Inventors: Shunji Kuwahara, Hiroki Fujisawa
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Patent number: 7902858Abstract: A calibration circuit includes: a replica buffer that drives a calibration terminal; a pre-emphasis circuit connected in parallel to the replica buffer; and an up-down counter that changes impedances of the replica buffer and the pre-emphasis circuit. A replica control circuit causes the replica buffer to conduct based on an impedance code, and a pre-emphasis control circuit causes the pre-emphasis circuit to conduct in an initial stage of a conducting period of the replica buffer. Thereby, even when an external resistor is shared among a plurality of semiconductor devices, for example, a voltage appearing in the calibration terminal can be stabilized at a higher speed.Type: GrantFiled: July 9, 2008Date of Patent: March 8, 2011Assignee: Elpida Memory, Inc.Inventors: Shunji Kuwahara, Hiroki Fujisawa
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Patent number: 7872493Abstract: In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK1 to both a hit determination circuit and a second clock gate circuit. The second clock gate circuit 110 passes through the first update clocks CLK1 until reception of a hit signal from the hit determination circuit and delivers second update clocks CLK2 to an up/down counter 106. The up/down counter 106 is operated by the second update clocks CLK2. With this structure, the second update clocks used for adjustment steps can be increased in number during the calibration period.Type: GrantFiled: May 20, 2009Date of Patent: January 18, 2011Assignee: Elpida Memory, Inc.Inventors: Shunji Kuwahara, Hiroki Fujisawa
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Publication number: 20100207680Abstract: To include two counter circuits that change impedances of two replica circuits, respectively, and an impedance adjustment control circuit that controls the counter circuits to update count values of the counter circuits. The impedance adjustment control circuit controls one of the counter circuits to finish updating the count value of the counter circuit in response to a change of the impedance of the corresponding replica circuit from a state of being lower than an impedance of an external resistor to a state of being higher than the impedance of the external resistor, and controls the other counter circuit to finish updating the count value of the other counter circuit in response to a change of the impedance of the other replica circuit from a state of being higher than the impedance of the former replica circuit to a state of being lower than the impedance of the former replica circuit. With this configuration, the adjust errors generated in the replica circuits are canceled.Type: ApplicationFiled: February 17, 2010Publication date: August 19, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Shunji KUWAHARA, Hiroki FUJISAWA
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Publication number: 20090289659Abstract: In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK1 to both a hit determination circuit and a second clock gate circuit. The second clock gate circuit 110 passes through the first update clocks CLK1 until reception of a hit signal from the hit determination circuit and delivers second update clocks CLK2 to an up/down counter 106. The up/down counter 106 is operated by the second update clocks CLK2. With this structure, the second update clocks used for adjustment steps can be increased in number during the calibration period.Type: ApplicationFiled: May 20, 2009Publication date: November 26, 2009Inventors: Shunji Kuwahara, Hiroki Fujisawa
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Publication number: 20090015312Abstract: A calibration circuit includes: a replica buffer that drives a calibration terminal; a pre-emphasis circuit connected in parallel to the replica buffer; and an up-down counter that changes impedances of the replica buffer and the pre-emphasis circuit. A replica control circuit causes the replica buffer to conduct based on an impedance code, and a pre-emphasis control circuit causes the pre-emphasis circuit to conduct in an initial stage of a conducting period of the replica buffer. Thereby, even when an external resistor is shared among a plurality of semiconductor devices, for example, a voltage appearing in the calibration terminal can be stabilized at a higher speed.Type: ApplicationFiled: July 9, 2008Publication date: January 15, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Shunji Kuwahara, Hiroki Fujisawa