Patents by Inventor Shunji Sasabe

Shunji Sasabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6497992
    Abstract: In order that reaction products of low vapor pressure may be prevented from being deposited on the side wall of a predetermined pattern when this pattern is to be formed by dry-etching a Pt film or a PZT film, a resist mask 54 having a rounded outer periphery at its head is used when the Pt film 53 deposited on a semiconductor substrate 50 is to be dry-etched. After this dry-etching, moreover, an overetching of a proper extent is performed to completely remove the side wall deposited film 55 which is left on the side of the pattern. The resist mask 54 is formed by exposing and developing a benzophenone novolak resist and subsequently by heating to set it while irradiating it, if necessary, with ultraviolet rays.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: December 24, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Yunogami, Shunji Sasabe, Kazuyuki Suko, Jun Abe, Takao Kumihashi, Fumio Murai
  • Patent number: 6057081
    Abstract: In order that reaction products of low vapor pressure may be prevented from being deposited on the side wall of a predetermined pattern when this pattern is to be formed by dry-etching a Pt film or a PZT film, a resist mask 54 having a rounded outer periphery at its head is used when the Pt film 53 deposited on a semiconductor substrate 50 is to be dry-etched. After this dry-etching, moreover, an overetching of a proper extent is performed to completely remove the side wall deposited film 55 which is left on the side of the pattern. The resist mask 54 is formed by exposing and developing a benzophenone novolak resist and subsequently by heating to set it while irradiating it, if necessary, with ultraviolet rays.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: May 2, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Yunogami, Shunji Sasabe, Kazuyuki Suko, Jun Abe, Takao Kumihashi, Fumio Murai
  • Patent number: 5972862
    Abstract: There is disclosed a cleaning liquid for producing a semiconductor device which comprises (A) fluorine-containing compound; (B) water-soluble or water-miscible organic solvent; and (C) inorganic acid and/or organic acid, optionally, further comprises (D) quaternary ammonium salt or (D') a specific organic carboxylic acid ammonium salt and/or an organic carboxylic acid amine salt; as well as a process for producing a semiconductor device by forming a resist pattern on a substrate equipped on the surface with an insulating film layer or a metallic electroconductive layer, forming a via hole or electric wiring by dry etching, removing the resist pattern by ashing treatment with oxygen plasma; and effecting an cleaning treatment with the above cleaning liquid. The above cleaning liquid and production process can readily remove the deposit polymer formed in the case of dry etching without impairing metallic film and insulating film.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: October 26, 1999
    Assignee: Mitsubishi Gas Chemical
    Inventors: Yoshimi Torii, Shunji Sasabe, Masayuki Kojima, Kazuhisa Usuami, Takafumi Tokunaga, Kazusato Hara, Yoshikazu Ohira, Tsuyoshi Matsui, Hideto Gotoh, Tetsuo Aoyama, Ryuji Hasemi, Hidetoshi Ikeda, Fukusaburo Ishihara, Ryuji Sotoaka
  • Patent number: 5235399
    Abstract: An apparatus for measuring the temperature of an object placed in a plasma by utilizing radiation includes measuring means for measuring the intensity of radiation from the object and the intensity of plasma light in different directions at the same time. The measuring means includes a first lens for receiving the radiation from the object and the plasma light, a second lens for converting the output beam of the first lens into parallel light rays, a third lens for focusing the parallel light rays, and an interference filter disposed rotatably between the second lens and the third lens.
    Type: Grant
    Filed: June 24, 1991
    Date of Patent: August 10, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Tatehito Usui, Tomoji Watanabe, Junichi Kobayashi, Takehiko Ooshima, Shunji Sasabe
  • Patent number: 5060045
    Abstract: Disclosed is a semiconductor integrated circuit device adopting a gate array scheme, having a plurality of layers of wiring formed by a Design Automation system. The device according to the present invention includes a semiconductor substrate having basic cell forming regions, the basic cell forming regions being spaced from each other with wiring channel regions between adjacent basic cell forming regions. The wiring includes at least first-layer wiring lines arranged overlying the wiring channel regions; second-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions; and third-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions. The first-, second- and third-layer wiring lines respectively extend in first, second and third directions, the second direction being different from the first direction.
    Type: Grant
    Filed: October 17, 1989
    Date of Patent: October 22, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Nobuo Owada, Hiroyuki Akimori, Takahisa Nitta, Tohru Kobayashi, Shunji Sasabe, Mikinori Kawaji, Osamu Kasahara
  • Patent number: 5021114
    Abstract: A sputter etching apparatus including a vacuum chamber provided with a gas supply system and an evacuator, a sputter etching electrode disposed within the vacuum chamber on which a substrate is disposed, a plasma generator for generating plasma by applying microwave energy and disposed in opposition to the sputter etching electrode, a voltage applying stud provided in association with the sputter etching electrode for causing ions in the plasma to impact against the substrate, a first power supply source provided in association with the plasma generator for generating the plasma, and a second power supply source provided independent of the first power supply source for supplying the voltage for causing the ions to impact against the substrate.
    Type: Grant
    Filed: July 19, 1988
    Date of Patent: June 4, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Saito, Yasumichi Suzuki, Shunji Sasabe, Kazuhiro Nakajima
  • Patent number: 4717462
    Abstract: A sputtering apparatus comprising an intermediate electrode having a plurality of openings disposed between a cathode and a substrate electrode.The directionality of the particles which are liberated from a target by the collision of ions against the target is made remarkably uniform by the presence of the intermediate electrode, and thus a thin film having a superior step coverage can be deposited on the substrate placed on the substrate electrode.
    Type: Grant
    Filed: October 24, 1986
    Date of Patent: January 5, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Homma, Sukeyoshi Tsunekawa, Shunji Sasabe