Patents by Inventor Shunji Sekimoto

Shunji Sekimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data erasing method, and memory apparatus having data erasing circuit using such method
    Patent number: 7023732
    Abstract: The present invention is to propose an data erasing method, a memory apparatus, and a data erasing circuit which are able to reduce the time required to boost the potential of the semiconductor substrate thereby to reduce the time required to erase data. Namely, a memory apparatus having a data erasing circuit that erases stored data by applying an erasing voltage between a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate is disclosed. In this case, the data erasing circuit boosts a potential of the semiconductor substrate side while placing the control gate into its floating state; and applies an erasing voltage between the semiconductor substrate and the control gate to make the potential of the control gate to a predetermined potential.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: April 4, 2006
    Assignee: Sony Corporation
    Inventors: Shunji Sekimoto, Tomohiro Namise
  • Data erasing method, and memory apparatus having data erasing circuit using such method
    Publication number: 20050012139
    Abstract: The present invention is to propose an data erasing method, a memory apparatus, and a data erasing circuit which are able to reduce the time required to boost the potential of the semiconductor substrate thereby to reduce the time required to erase data. Namely, a memory apparatus having a data erasing circuit that erases stored data by applying an erasing voltage between a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate is disclosed. In this case, the data erasing circuit boosts a potential of the semiconductor substrate side while placing the control gate into its floating state; and applies an erasing voltage between the semiconductor substrate and the control gate to make the potential of the control gate to a predetermined potential.
    Type: Application
    Filed: June 29, 2004
    Publication date: January 20, 2005
    Inventors: Shunji Sekimoto, Tomohiro Namise