Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.

Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by the controller processor; and a plurality of load boards respectively coupled to the plurality of programmable accelerator circuits. The plurality of load boards can apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. The plurality of programmable accelerator circuits can provide input test signals and capture output test signals. In one exemplary implementation, each of the plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from the respective DUT; and sideband connectors. The sideband connectors receive test related information from the DUT.

Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT,a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.

Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system comprises: a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by said controller processor, said plurality of programmable accelerator circuits for providing input test signals and for capturing output test signals; and a plurality of load boards respectively coupled to said plurality of programmable accelerator circuits, said plurality of load boards for applying said input test signals to a plurality of devices under test (DUTs) and for capturing said output test signals therefrom. In one exemplary implementation, each of said plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from said respective DUT; and sideband connectors. The sideband connectors receive test related information from said DUT.