Patents by Inventor Shunji Yasumura

Shunji Yasumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6743708
    Abstract: An interlayer insulation film (31) on a plug (11) is etched using a silicon nitride film (32) used in pattern etching of a bit line (12) as a hard mask such that the plug (11) projects into a groove (40). Another silicon nitride film (33) is provided to cover an exposed surface of the groove (40), the bit line (12) and the silicon nitride film (32), thereby forming another interlayer insulation film (34) on the silicon nitride film (33) to fill the groove (40). The silicon nitride films (33, 32) are used as an etching stopper to etch the interlayer insulation film (34) above the plug (11). The silicon nitride film (33) on the plug (11) is etched to expose the plug (11) into a recess.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: June 1, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shinya Watanabe, Shunji Yasumura
  • Patent number: 6583461
    Abstract: The semiconductor device comprises a capacitor electrode defining openings which are made in each insulating layer, are communicated with one another and have different diameters at least at their coupling portions, the capacitor electrode is formed to extend along the surfaces of the openings.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: June 24, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuichi Yokoyama, Shunji Yasumura
  • Publication number: 20030111668
    Abstract: An interlayer insulation film (31) on a plug (11) is etched using a silicon nitride film (32) used in pattern etching of a bit line (12) as a hard mask such that the plug (11) projects into a groove (40). Another silicon nitride film (33) is provided to cover an exposed surface of the groove (40), the bit line (12) and the silicon nitride film (32), thereby forming another interlayer insulation film (34) on the silicon nitride film (33) to fill the groove (40). The silicon nitride films (33, 32) are used as an etching stopper to etch the interlayer insulation film (34) above the plug (11). The silicon nitride film (33) on the plug (11) is etched to expose the plug (11) into a recess.
    Type: Application
    Filed: October 9, 2002
    Publication date: June 19, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Shinya Watanabe, Shunji Yasumura
  • Patent number: 6580113
    Abstract: There is described a high-integration, superior-power-efficiency semiconductor device having a storage node, whose structure is suitable for enabling high-yield and inexpensive manufacture. A plurality of transfer gates are formed on a silicon substrate. An interlayer film is provided so as to cover the transfer gates. A hollow node is formed from conductive material on the interlayer film. A contact hole is formed so as to penetrate through the interlayer film without exposing the transfer gate, as well as to expose the surface of the silicon substrate within the hollow node. A conductive layer is formed so as to cover the interior surface of the contact hole to a predetermined thickness in the region ranging from the interior surface of the hollow node to the exposed portion of the silicon substrate.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: June 17, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinya Watanabe, Shunji Yasumura
  • Publication number: 20020028553
    Abstract: The semiconductor device comprises a capacitor electrode defining openings which are made in each insulating layer, are communicated with one another and have different diameters at least at their coupling portions, the capacitor electrode is formed to extend along the surfaces of the openings.
    Type: Application
    Filed: August 27, 2001
    Publication date: March 7, 2002
    Inventors: Yuichi Yokoyama, Shunji Yasumura
  • Publication number: 20010040251
    Abstract: There is described a high-integration, superior-power-efficiency semiconductor device having a storage node, whose structure is suitable for enabling high-yield and inexpensive manufacture. A plurality of transfer gates are formed on a silicon substrate. An interlayer film is provided so as to cover the transfer gates. A hollow node is formed from conductive material on the interlayer film. A contact hole is formed so as to penetrate through the interlayer film without exposing the transfer gate, as well as to expose the surface of the silicon substrate within the hollow node. A conductive layer is formed so as to cover the interior surface of the contact hole to a predetermined thickness in the region ranging from the interior surface of the hollow node to the exposed portion of the silicon substrate.
    Type: Application
    Filed: June 28, 1999
    Publication date: November 15, 2001
    Inventors: SHINYA WATANABE, SHUNJI YASUMURA
  • Patent number: 6033952
    Abstract: A semiconductor device manufacturing method which involves a fewer number of manufacturing processes and which eliminates the use of expensive high precision stepper and half-tone mask, or the like, by employing a simplified process flow, in which method an identical mask is reused to ensure registration margin without involving a high-resolution process. A contact hole requires solely a minimum diameter of 0.30 .mu.m or thereabouts, thereby resulting in and added margin for the minimum diameter and eliminating a process for reducing a hole diameter. Even if the hole diameter has a deviation of about 0.05 .mu.m, contact can be established with a silicon substrate, thereby eliminating a necessity for an expensive, high precision stepper which has been required for ensuring a registration margin.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: March 7, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shunji Yasumura, Shinya Watanabe