Patents by Inventor Shunji Yoshitake

Shunji Yoshitake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8829488
    Abstract: Provided is a laminate containing a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×1018 cm3 or more.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
  • Publication number: 20130020681
    Abstract: Provided is a laminate comprising a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×10? cm or more.
    Type: Application
    Filed: August 27, 2012
    Publication date: January 24, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuyoshi FURUKAWA, Yasuhiko Akaike, Shunji Yoshitake
  • Publication number: 20080308827
    Abstract: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1-yAly)1-xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45?x?0.
    Type: Application
    Filed: March 5, 2008
    Publication date: December 18, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
  • Patent number: 7364982
    Abstract: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1-yAly)1-xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45<x<0.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: April 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
  • Publication number: 20070111473
    Abstract: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1-yAly)1-xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45<x<0.
    Type: Application
    Filed: January 10, 2007
    Publication date: May 17, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
  • Patent number: 7217635
    Abstract: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1?yAly)1?xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45<x<0.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: May 15, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
  • Patent number: 7037738
    Abstract: There is disclosed a semiconductor light-emitting element comprising a substrate having a first surface and a second surface, a semiconductor laminate formed on the first surface of the substrate and containing a light-emitting layer and a current diffusion layer having a light-extracting surface. The light-emitting element is provided with a light-extracting surface which is constituted by a finely recessed/projected surface, 90% of which is constructed such that the height of the projected portion thereof having a cone-like configuration is 100 nm or more, and the width of the base of the projected portion is within the range of 10-500 nm.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: May 2, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Sugiyama, Kenichi Ohashi, Atsuko Yamashita, Shoichi Washizuka, Yasuhiko Akaike, Shunji Yoshitake, Koji Asakawa, Katsumi Egashira, Akira Fujimoto
  • Publication number: 20050145864
    Abstract: There is disclosed a semiconductor light-emitting element comprising a substrate having a first surface and a second surface, a semiconductor laminate formed on the first surface of the substrate and containing a light-emitting layer and a current diffusion layer having a light-extracting surface. The light-emitting element is provided with a light-extracting surface which is constituted by a finely recessed/projected surface, 90% of which is constructed such that the height of the projected portion thereof having a cone-like configuration is 100 nm or more, and the width of the base of the projected portion is within the range of 10-500 nm.
    Type: Application
    Filed: February 10, 2005
    Publication date: July 7, 2005
    Inventors: Hitoshi Sugiyama, Kenichi Ohashi, Atsuko Yamashita, Shoichi Washizuka, Yasuhiko Akaike, Shunji Yoshitake, Koji Asakawa, Katsumi Egashira, Akira Fujimoto
  • Patent number: 6914923
    Abstract: A semiconductor laser includes a substrate, a double hetero structure portion formed on the substrate, the double hetero structure including a first clad layer formed on the substrate, an active layer formed on the first clad layer and a second clad layer formed on the active layer, the second clad layer having a stripe-form projection on an upper surface thereof, the projection having an upper portion whose sidewalls are substantially vertically formed on the surface of the substrate and a step-shaped lower portion whose line width is larger than that of the upper portion, and a current blocking layer formed extending from side surfaces of the projection to the upper surface of the second clad layer except an upper surface of the projection.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: July 5, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunji Yoshitake, Toshiyuki Terada, Akira Tanaka
  • Patent number: 6900473
    Abstract: A semiconductor light emitting device is disclosed in which a semiconductor multilayer structure including a light emitting layer is formed on a substrate and light is output from the opposite surface of the semiconductor multilayer structure from the substrate. The light output surface is formed with a large number of protrusions in the form of cones or pyramids. To increase the light output efficiency, the angle between the side of each protrusion and the light output surface is set to between 30 and 70 degrees.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: May 31, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunji Yoshitake, Hideki Sekiguchi, Atsuko Yamashita, Kazuhiro Takimoto, Koichi Takahashi
  • Publication number: 20050066880
    Abstract: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1-yAly)1-xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45<x<0.
    Type: Application
    Filed: October 12, 2004
    Publication date: March 31, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
  • Publication number: 20050058170
    Abstract: Disclosed is a semiconductor laser element including: a double heterojunction structure having a p-type clad layer; a second p-type clad layer formed on the double heterojunction structure, having a first dopant and a ridge shape; a p-type contact layer formed on the second p-type clad layer, having a second dopant whose diffusion velocity is slower than that of the first dopant; a dielectric film covering a side surface of the second p-type clad layer and the p-type contact layer, and a surface on which the second p-type clad layer is not formed on the double heterojunction structure; and a p-side electrode formed on the p-type contact layer. Meanwhile, disclosed is a semiconductor laser element including a similar double heterojunction structure, a second p-type clad layer, a p-type contact layer, and a p-side electrode, with end faces of cleavages of the double heterojunction structure thereof being an unmarshalled layer structure.
    Type: Application
    Filed: September 13, 2004
    Publication date: March 17, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Itoh, Toshiyuki Terada, Shunji Yoshitake
  • Patent number: 6815312
    Abstract: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1−yAly)1−xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45<x<0.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: November 9, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
  • Patent number: 6791117
    Abstract: A semiconductor light emitting device is disclosed, which comprises a substrate, and a multi-layer semiconductor film formed on the substrate, the multi-layer semiconductor film including a plurality of semiconductor layers overlaid on the substrate, the semiconductor layers having a light emission layer for emitting a light, wherein the light is picked up at a first side of the multi-layer semiconductor film, which is a side opposite to the substrate, wherein a pattern having a light pickup surface is formed on a light emitting portion of the multi-layer semiconductor film, the light pickup surface is in a (111) plane or a plane in the vicinity of the (111) plane, and an unevenness is formed on the light pickup surface.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunji Yoshitake, Koichi Takahashi, Shinji Nunotani, Kenichi Ohashi
  • Publication number: 20040022287
    Abstract: A semiconductor laser includes a substrate, a double hetero structure portion formed on the substrate, the double hetero structure including a first clad layer formed on the substrate, an active layer formed on the first clad layer and a second clad layer formed on the active layer, the second clad layer having a stripe-form projection on an upper surface thereof, the projection having an upper portion whose sidewalls are substantially vertically formed on the surface of the substrate and a step-shaped lower portion whose line width is larger than that of the upper portion, and a current blocking layer formed extending from side surfaces of the projection to the upper surface of the second clad layer except an upper surface of the projection.
    Type: Application
    Filed: May 28, 2003
    Publication date: February 5, 2004
    Inventors: Shunji Yoshitake, Toshiyuki Terada, Akira Tanaka
  • Publication number: 20030178626
    Abstract: There is disclosed a semiconductor light-emitting element comprising a substrate having a first surface and a second surface, a semiconductor laminate formed on the first surface of the substrate and containing a light-emitting layer and a current diffusion layer having a light-extracting surface. The light-emitting element is provided with a light-extracting surface which is constituted by a finely recessed/projected surface, 90% of which is constructed such that the height of the projected portion thereof having a cone-like configuration is 100 nm or more, and the width of the base of the projected portion is within the range of 10-500 nm.
    Type: Application
    Filed: January 17, 2003
    Publication date: September 25, 2003
    Inventors: Hitoshi Sugiyama, Kenichi Ohashi, Atsuko Yamashita, Shoichi Washizuka, Yasuhiko Akaike, Shunji Yoshitake, Koji Asakawa, Katsumi Egashira, Akira Fujimoto
  • Publication number: 20030132445
    Abstract: A semiconductor light emitting device is disclosed, which comprises a substrate, and a multi-layer semiconductor film formed on the substrate, the multi-layer semiconductor film including a plurality of semiconductor layers overlaid on the substrate, the semiconductor layers having a light emission layer for emitting a light, wherein the light is picked up at a first side of the multi-layer semiconductor film, which is a side opposite to the substrate, wherein a pattern having a light pickup surface is formed on a light emitting portion of the multi-layer semiconductor film, the light pickup surface is in a (111) plane or a plane in the vicinity of the (111) plane, and an unevenness is formed on the light pickup surface.
    Type: Application
    Filed: January 14, 2003
    Publication date: July 17, 2003
    Inventors: Shunji Yoshitake, Koichi Takahashi, Shinji Nunotani, Kenichi Ohashi
  • Publication number: 20020195609
    Abstract: A semiconductor light emitting device is disclosed in which a semiconductor multilayer structure including a light emitting layer is formed on a substrate and light is output from the opposite surface of the semiconductor multilayer structure from the substrate. The light output surface is formed with a large number of protrusions in the form of cones or pyramids. To increase the light output efficiency, the angle between the side of each protrusion and the light output surface is set to between 30 and 70 degrees.
    Type: Application
    Filed: June 25, 2002
    Publication date: December 26, 2002
    Inventors: Shunji Yoshitake, Hideki Sekiguchi, Atsuko Yamashita, Kazuhiro Takimoto, Koichi Takahashi
  • Publication number: 20020185648
    Abstract: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1-yAly)1-xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45<x<0.
    Type: Application
    Filed: August 5, 2002
    Publication date: December 12, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
  • Patent number: 6465809
    Abstract: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1−yAly)1−xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45<x<0.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: October 15, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake