Abstract: A single crystal multi-element positive electrode material and a preparation method therefor, and a lithium ion battery. The ratio of the length of the longest diagonal line to the length of the shortest diagonal line of the single crystal particles of the single crystal multi-element positive electrode material measured by an SEM is roundness R, and R?1; and D10, D50 and D90 of the single crystal particles of the single crystal multi-element positive electrode material satisfy: K90=(D90?D10)/D50, and the product of K90 and R is 1.20-1.40. The single crystal multi-element positive electrode material is more round and regular in morphology, the single crystal particles have uniform size, less agglomeration and less adhesion. The material has the characteristics of high compaction density, good rate capability and excellent cycle performance.

Abstract: The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area of a bus function model unit; reading, by a software test instance, the random parameters and the random controls through the central processing unit, and configuring a test of the system on chip; storing execution status information of the software test instance in the storage area; reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude having been tested scenarios, and converting the execution status information into coverage data for coverage analysis.

Abstract: The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.

Abstract: The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.

Abstract: The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area of a bus function model unit; reading, by a software test instance, the random parameters and the random controls through the central processing unit, and configuring a test of the system on chip; storing execution status information of the software test instance in the storage area; reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude having been tested scenarios, and converting the execution status information into coverage data for coverage analysis.