Abstract: A semiconductor device includes a flip-flop circuit, a control line, a first P-type transistor and a first non-volatile storage element, and a second P-type transistor and a second non-volatile storage element. The flip-flop circuit has a circular structure in which a first inverter circuit, a first connection line including a first node, a second inverter circuit, and a second connection line including a second node are coupled in order. The first P-type transistor and the first non-volatile storage element are coupled together in series between the first node and the control line. The second P-type transistor and the second non-volatile storage element are coupled together in series between the second node and the control line. The non-volatile storage element is a magnetic tunnel junction element including a pinned layer, a tunnel barrier layer, and a free layer arranged in order from a position close to the control line.

Abstract: A semiconductor device includes a flip-flop circuit, a control line, a first P-type transistor and a first non-volatile storage element, and a second P-type transistor and a second non-volatile storage element. The flip-flop circuit has a circular structure in which a first inverter circuit, a first connection line including a first node, a second inverter circuit, and a second connection line including a second node are coupled in order. The first P-type transistor and the first non-volatile storage element are coupled together in series between the first node and the control line. The second P-type transistor and the second non-volatile storage element are coupled together in series between the second node and the control line. The non-volatile storage element is a magnetic tunnel junction element including a pinned layer, a tunnel barrier layer, and a free layer arranged in order from a position close to the control line.

Abstract: A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament.

Abstract: A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament.

Abstract: Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), comprising: inverting a state of data for input to one or more columns of the array; and storing the inverted data in one or more memory cells of the one or more columns.

Abstract: Processors arranged in a multi-processor configuration for substantially parallel operations receive their initialization data in order to start operations, such as graphics computations, real-time multimedia streaming, etc. Due to a change in the processing load, one or more processors might be deactivated. Subsequently, the load increases to such a level that requires all or some of the deactivated processors to be active again. In this case, the boot-up process of the entire system is not carried out as it would be time-consuming and wasteful; instead, responsive to a control signal only those processors that were previously in inactive mode are re-initialized by selecting a configuration data supplied by another processor, controller or any other intelligent programmable device.

Abstract: Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge, logic high voltage level during operations in which a logic low level is written into the anti-parallel storage circuit.

Abstract: Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge level during operations in which a logic one is read from the anti-parallel storage circuit.

Abstract: Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge, logic high voltage level during operations in which a logic low level is written into the anti-parallel storage circuit.

Abstract: Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge level during operations in which a logic one is read from the anti-parallel storage circuit.

Abstract: Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), including: mirroring logic values of at least one of the bit lines to a global bit line; driving the global bit line to a pre-charge logic value in response to a clock signal that cycles at least one time during successive read and write operations to the memory cell; maintaining the global bit line at the pre-charge logic value during a write operation in which a logic value is written to the bit line that is opposite to the pre-charge logic value.

Abstract: Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), comprising: inverting a state of data for input to one or more columns of the array; and storing the inverted data in one or more memory cells of the one or more columns.

Abstract: A semiconductor memory device having a dummy memory cell and a reading method of the same, wherein provision is made of a memory cell 11 connected to a word line WL and a pair of bit lines BL and xBL, a dummy memory cell 12 connected to a word line WL and a pair of dummy bit lines DBL and xDBL, and a word line driver 13 for activating the word line at a common timing, and when the data is read out from the memory cell, a timing of the reading of the data is determined in accordance with a level of the dummy bit lines connected to the dummy memory, and when a voltage difference of a pair of dummy bit lines becomes a threshold voltage, the word line driver deactivates the word line and precharges the dummy bit lines.

Abstract: Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), including: mirroring logic values of at least one of the bit lines to a global bit line; driving the global bit line to a pre-charge logic value in response to a clock signal that cycles at least one time during successive read and write operations to the memory cell; maintaining the global bit line at the pre-charge logic value during a write operation in which a logic value is written to the bit line that is opposite to the pre-charge logic value.

Abstract: Processors arranged in a multi-processor configuration for substantially parallel operations receive their initialization data in order to start operations, such as graphics computations, real-time multimedia streaming, etc. Due to a change in the processing load, one or more processors might be deactivated. Subsequently, the load increases to such a level that requires all or some of the deactivated processors to be active again. In this case, the boot-up process of the entire system is not carried out as it would be time-consuming and wasteful; instead, responsive to a control signal only those processors that were previously in inactive mode are re-initialized by selecting a configuration data supplied by another processor, controller or any other intelligent programmable device.

Abstract: Methods and apparatus provide for pre-charging a bit line and a complementary bit line of an SRAM memory cell of the SRAM memory to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the memory cell.

Abstract: A semiconductor memory device having a dummy memory cell and a reading method of the same, wherein provision is made of a memory cell 11 connected to a word line WL and a pair of bit lines BL and xBL, a dummy memory cell 12 connected to a word line WL and a pair of dummy bit lines DBL and xDBL, and a word line driver 13 for activating the word line at a common timing, and when the data is read out from the memory cell, a timing of the reading of the data is determined in accordance with a level of the dummy bit lines connected to the dummy memory, and when a voltage difference of a pair of dummy bit lines becomes a threshold voltage, the word line driver deactivates the word line and precharges the dummy bit lines.

Abstract: Methods and apparatus provide for pre-charging a bit line and a complementary bit line of an SRAM memory cell of the SRAM memory to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the memory cell.