Abstract: The present invention provides a method and an apparatus for controlling initial transients in a frequency synthesizer by controlling the start-up sequence of the device. The start-up sequence comprises several steps. The voltage controlled oscillator(s) (VCO) is reset so that the VCO(s) are in a known state during start-up. The charge pump and phase detector of phase-locked loop (PLL) are disabled. New data values are loaded into counter(s)/register(s) that control the frequency of the VCO(s). Also, a data value is provided to a digital-to-analog converter (DAC) to set the data rate for the PLL. A fixed amount of time is provided as a delay for the DAC to settle (i.e., 1.6 .mu.s). Divide-by-M and divide-by-N counters are then enabled. Also, the phase detector of the phase-locked loop (PLL) is enabled. The VCO is then restarted.

Abstract: The present invention provides a high speed, all CMOS comparator utilizing positive feedback and DC voltage clamping. The circuit comprises two source-coupled PMOS transistors with their sources coupled to a current source or a supply voltage. A third PMOS transistor is coupled between the source of the first PMOS transistor and a terminal of a current mirror. The gate of this third PMOS transistor is coupled to the output node in such a way as to provide positive feedback to the circuit. As the negative input voltage becomes lower than the positive input voltage, the current passing through the second PMOS transistor increases and the current passing through the first PMOS transistor decreases. As the output node increases in voltage, the equivalent resistance of the third PMOS transistor increases, thus decreasing the current through the first PMOS transistor. This acts to increase the current being provided to the output node and increases the drive characteristics of the circuit.

Abstract: The present invention is a constant current source whose magnitude is proportional to capacitor values, reference voltage and input frequency. A frequency divider provides a plurality of signals to one of a plurality of capacitor switches located within a charge generator. The outputs of the capacitor switches are combined to provide a known charge Q.sub.i to an output generator at regular intervals, t.sub.0 =1/F.sub.in. The output generator produces an output current I.sub.out =Q.sub.i /t.sub.0 =C.sub.i *V.sub.bg *F.sub.in, where C.sub.i is a capacitor value, V.sub.bg is a reference voltage, and F.sub.in is the input frequency. A controller provides a control signal to the output generator to limit variations in the output current I.sub.out. The preferred embodiment may be used in conjunction with process invariant circuits in a variety of semiconductor technologies: CMOS, Bipolar, BiCMOS and GAS. In one embodiment, the present invention is used in conjuction with a timer/delay circuit.

Abstract: The present invention provides a linearized and delay compensated all CMOS voltage controlled oscillator. A transconductance converter receives a control voltage input and provides a control current to a current controlled ramping circuit that is responsible for providing two ramping voltage outputs to the positive inputs of two comparators. These comparators compare the ramping voltages to a threshold voltage and provide pulses to a latch when the ramping voltages cross the threshold voltage. The latch provides the oscillating output of the circuit which is fed back to the current controlled ramping circuit for switching purposes. A compensation loop receives both the oscillating output of the latch and the control current as inputs and provides the threshold voltage to the comparators. The compensation loop contains a similar current controlled ramping circuit which provides ramping outputs identical to those of the first current controlled ramping circuit.

Abstract: Disclosed is a process for the preparation of a copolymer, which comprises propagating cells of a bacterium having a capacity of producing poly-3-hydroxybutyrate mainly at a former stage, synthesizing and accumulating in the cells a copolymer comprising D-3-hydroxybutyrate and D-3-hydroxyvalerate by contacting the bacterium with a mixture of a carbon source utilizable by the bacterium and a primary alcohol having 3 to 7 carbon atoms, or with a primary alcohol having 3 to 7 carbon atoms, at a latter stage, and recovering the copolymer from the cells. According to this process, a copolymer comprising D-3-hydroxybutyrate and D-3-hydroxyvalerate can be manufactured in a large quantity at a low cost.

Abstract: The present invention provides a linearized and delay compensated all CMOS voltage controlled oscillator. A transconductance converter receives a control voltage input and provides a control current to a current controlled ramping circuit that is responsible for providing two ramping voltage outputs to the positive inputs of two comparators. These comparators compare the ramping voltages to a threshold voltage and provide pulses to a latch when the ramping voltages cross the threshold voltage. The latch provides the oscillating output of the circuit which is fed back to the current controlled ramping circuit for switching purposes. A compensation loop receives both the oscillating output of the latch and the control current as inputs and provides the threshold voltage to the comparators. The compensation loop contains a similar current controlled ramping circuit which provides ramping outputs identical to those of the first current controlled ramping circuit.

Abstract: A zero-phase restart circuit that provides a new circuit element in the path of the incoming data signal in order to delay the data signal by an amount equal to the delay caused by the restart circuitry. This ensures that the phase difference between the two signals will be zero at restart and thus effectively cancels out the residual error seen with the prior art. This technique remains effective well into higher data rates. The advantages of the present invention allows the circuit to operate near its limit without suffering large transients on the VCO control voltage and the VCO frequency. The overall system will not be limited by the transient response on the VCO control voltage nor the VCO frequency. It allows for higher operating speeds of data. Further, the new method will allow the system to better tolerate the jitter of the incoming data such that the restrictions on the jitter performance of the incoming data can be reduced substantially, i.e., allow more jitter to exist on the data.