Patents by Inventor Shunsuke ASANAO

Shunsuke ASANAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of forming the same
    Patent number: 11581278
    Abstract: A semiconductor device includes a first layer including a plurality of wirings arranged in line and space layout and a second layer including a pad electrically connected to at least one of the wirings, wherein the wirings and the pads are patterned by different lithographic processes.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hidenori Yamaguchi, Shunsuke Asanao, Katsumi Koge, Shigeharu Nishimura
  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20220122931
    Abstract: A semiconductor device includes a first layer including a plurality of wirings arranged in line and space layout and a second layer including a pad electrically connected to at least one of the wirings, wherein the wirings and the pads are patterned by different lithographic processes.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 21, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Hidenori Yamaguchi, Shunsuke Asanao, Katsumi Koge, Shigeharu Nishimura
  • Semiconductor device having a reduced pitch between lead-out wirings
    Patent number: 11049809
    Abstract: One semiconductor device includes first to fourth wirings disposed within a prescribed interval in a first direction, extending in a second direction, and arranged at a first pitch in the first direction, first to third lead-out wirings disposed within the prescribed interval in the first direction, extending in the second direction, and arranged at a second pitch in the first direction, a bridge part disposed between the first lead-out wiring, and the second lead-out wiring, and connected to the first lead-out wiring, and the second lead-out wiring, a first contact part in contact with at least one part of the bridge part, and a second contact part in contact with the third lead-out wiring. One of either the first lead-out wiring, or the second lead-out wiring is connected to the second wiring, and the third lead-out wiring is connected to the fourth wiring.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 29, 2021
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Shunsuke Asanao
  • SEMICONDUCTOR DEVICE
    Publication number: 20200258835
    Abstract: One semiconductor device includes first to fourth wirings disposed within a prescribed interval in a first direction, extending in a second direction, and arranged at a first pitch in the first direction, first to third lead-out wirings disposed within the prescribed interval in the first direction, extending in the second direction, and arranged at a second pitch in the first direction, a bridge part disposed between the first lead-out wiring, and the second lead-out wiring, and connected to the first lead-out wiring, and the second lead-out wiring, a first contact part in contact with at least one part of the bridge part, and a second contact part in contact with the third lead-out wiring. One of either the first lead-out wiring, or the second lead-out wiring is connected to the second wiring, and the third lead-out wiring is connected to the fourth wiring.
    Type: Application
    Filed: March 31, 2020
    Publication date: August 13, 2020
    Inventor: Shunsuke Asanao
  • Semiconductor device having a reduced pitch between lead-out wirings
    Patent number: 10615121
    Abstract: One semiconductor device includes first to fourth wirings disposed within a prescribed interval in a first direction, extending in a second direction, and arranged at a first pitch in the first direction, first to third lead-out wirings disposed within the prescribed interval in the first direction, extending in the second direction, and arranged at a second pitch in the first direction, a bridge part disposed between the first lead-out wiring, and the second lead-out wiring, and connected to the first lead-out wiring, and the second lead-out wiring, a first contact part in contact with at least one part of the bridge part, and a second contact part in contact with the third lead-out wiring. One of either the first lead-out wiring, or the second lead-out wiring is connected to the second wiring, and the third lead-out wiring is connected to the fourth wiring.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: April 7, 2020
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Shunsuke Asanao
  • SEMICONDUCTOR DEVICE
    Publication number: 20160043031
    Abstract: One semiconductor device includes first to fourth wirings disposed within a prescribed interval in a first direction, extending in a second direction, and arranged at a first pitch in the first direction, first to third lead-out wirings disposed within the prescribed interval in the first direction, extending in the second direction, and arranged at a second pitch in the first direction, a bridge part disposed between the first lead-out wiring, and the second lead-out wiring, and connected to the first lead-out wiring, and the second lead-out wiring, a first contact part in contact with at least one part of the bridge part, and a second contact part in contact with the third lead-out wiring. One of either the first lead-out wiring, or the second lead-out wiring is connected to the second wiring, and the third lead-out wiring is connected to the fourth wiring.
    Type: Application
    Filed: April 8, 2014
    Publication date: February 11, 2016
    Inventor: Shunsuke ASANAO