Abstract: There is provided a solid electrolytic capacitor which can increase an electrostatic capacitance and reduce ESR characteristics, and a method of manufacturing the solid electrolytic capacitor. The solid electrolytic capacitor has: a dielectric oxide film formed on a surface of an anode body having fine pores; a cathode body opposing to the anode body; and conductive polymer layers formed inside the fine pores and including amines and water-soluble self-doped conductive polymers having sulfonic acid groups. The self-doped conductive polymers are held in a good state inside fine pores such as etching pits, so that the electrostatic capacitance increases and ESR characteristics are reduced.

Abstract: There is provided a solid electrolytic capacitor which can increase an electrostatic capacitance and reduce ESR characteristics, and a method of manufacturing the solid electrolytic capacitor. The solid electrolytic capacitor has: a dielectric oxide film formed on a surface of an anode body having fine pores; a cathode body opposing to the anode body; and conductive polymer layers formed inside the fine pores and including amines and water-soluble self-doped conductive polymers having sulfonic acid groups. The self-doped conductive polymers are held in a good state inside fine pores such as etching pits, so that the electrostatic capacitance increases and ESR characteristics are reduced.

Abstract: The object of the present invention is to make parts and kinds of liquid crystal display devices in common for cope stably and flexibly with commercial products of computer makers and television makers which have been promoted in various kinds, for simplifying maintenance of a liquid crystal display unit mounted on computers, display monitors therefor or televisions, and preferably for enabling to omit positional adjustment of a light source unit and a liquid crystal display panel during the maintenance of the liquid crystal display device.

Abstract: An output signal from a level detection circuit that detects a super VIH (normal logical high voltage level) condition is set to a valid state or to an invalid state by a force circuit and is applied to a test control circuit. A test mode with the super VIH (SVIH) condition can be entered efficiently, while the possibility of an erroneous entry on the user side and constraints of the test apparatus upon serial test entry are suppressed.

Abstract: An output signal from a level detection circuit that detects a super VIH(normal logical high voltage level) condition is set to a valid state or to an invalid state by a force circuit and is applied to a test control circuit. A test mode with the super VIH (SVIH) condition can be entered efficiently, while the possibility of an erroneous entry on the user side and constraints of the test apparatus upon serial test entry are suppressed.

Abstract: A semiconductor memory device includes a sense amplifier provided for the bit lines. To the sense amplifier, an internal power supply voltage and a negative voltage or a ground voltage are supplied. In the normal operation mode, first and second transistors are turned on, and the bit line is amplified to the internal power supply voltage or the ground voltage. In the test mode, first and third transistors turn on, and the bit line is amplified to the power supply voltage or the negative voltage. Thus, potential difference between adjacent storage nodes is increased.

Abstract: A semiconductor memory device includes a sense amplifier provided for the bit lines. To the sense amplifier, an internal power supply voltage and a negative voltage or a ground voltage are supplied. In the normal operation mode, first and second transistors are turned on, and the bit line is amplified to the internal power supply voltage or the ground voltage. In the test mode, first and third transistors turn on, and the bit line is amplified to the power supply voltage or the negative voltage. Thus, potential difference between adjacent storage nodes is increased.

Abstract: A semiconductor storage device capable of detecting a high resistance shortcircuit between a storage node of a memory cell and a gate in a transistor of the memory cell. A sense amplifier activating signal generating circuit section 13 in a ROW control section 2 delays, by a predetermined time, a timing for activating sense amplifier activating signals SON and ZSOP in a test mode in which a High-level test mode signal TM is input, delays, by a predetermined time, a timing for activating each of the sense amplifiers of the sense amplifier section 3, and detects a high resistance shortcircuit caused between a storage node SN in the memory cell and a gate TG of the transistor.