Abstract: A random number generation device, comprising: a random number generation unit for generating random numbers; a random number generation control unit for providing parameters for enabling the random generation unit to generate random numbers; and a randomness determination unit for determining the randomness of each generated random number, wherein if the randomness of a generated random number does not meet a predetermined condition, the random number generation control unit updates the parameters for generating a random number to enable the random number generation unit to generate a new random number.

Abstract: A power supply circuit for supplying power to a load includes an antenna which receives electric power, a rectifier coupled to the antenna and configured to convert an alternating voltage supplied from the antenna into a direct-current voltage, a voltage step-down circuit which steps down the direct-current voltage to generate an output voltage for provision to the load, a regulator which controls a resistance connected between the output voltage and a ground voltage in parallel with the load, thereby controlling a voltage level of the output voltage.

Abstract: A data processing apparatus and card-sized data processing device that consume less power and operate more reliably. An antenna captures a radio wave sent from an external reader/writer device, and a receiver converts it into an electrical signal. From this electrical signal, a first power supply circuit produces a first supply voltage for use in analog circuits. A second power supply circuit produces a second supply voltage that is different from the first supply voltage, for use in memory circuits. A third power supply circuit produces a third supply voltage that is different from the other voltages, for use in digital circuits. The memory and digital circuits thus operate with different supply voltages optimized for their individual requirements. Total power consumption of the device is reduced by lowering the voltage for the digital circuits, including MPU, while giving a higher voltage to the memory circuits.

Abstract: A power supply circuit for supplying power to a load includes an antenna which receives electric power, a rectifier coupled to the antenna and configured to convert an alternating voltage supplied from the antenna into a direct-current voltage, a voltage step-down circuit which steps down the direct-current voltage to generate an output voltage for provision to the load, a regulator which controls a resistance connected between the output voltage and a ground voltage in parallel with the load, thereby controlling a voltage level of the output voltage.

Abstract: When information about an encrypting/decrypting method is received, it is complied with a library. A mapping data object that represents the structure of the circuit is generated. The mapping data object is written to a programmable logic device/unit. When the programmable logic device/unit is used for an encrypting/decrypting circuit, an encrypting/decrypting system that can flexibly change an algorithm at high speed can be accomplished.

Abstract: A data processing apparatus and card-sized data processing device that consume less power and operate more reliably. An antenna captures a radio wave sent from an external reader/writer device, and a receiver converts it into an electrical signal. From this electrical signal, a first power supply circuit produces a first supply voltage for use in analog circuits. A second power supply circuit produces a second supply voltage that is different from the first supply voltage, for use in memory circuits. A third power supply circuit produces a third supply voltage that is different from the other voltages, for use in digital circuits. The memory and digital circuits thus operate with different supply voltages optimized for their individual requirements. Total power consumption of the device is reduced by lowering the voltage for the digital circuits, including MPU, while giving a higher voltage to the memory circuits.

Abstract: A semiconductor integrated circuit includes a memory which stores secret data, a bus which is connected to the memory and transfers an encrypted address and encrypted data, a processing unit which encrypts what is to be transmitted to the bus based on an encryption key, and decrypts what is received from the bus based on the encryption key, thereby accessing the memory, an encryption/decryption circuit which is situated between the bus and the memory, and which decrypts what is received from the bus based on the encryption key and encrypts what is transmitted to the bus based on the encryption key when the processing unit accesses the memory, and an updating circuit which performs a process for updating the encryption key at predetermined intervals.

Abstract: A device capable of externally setting and modifying internal functions and a data processing apparatus using such a device are provided, outside the data processing apparatus, with a function data setting unit for reading and writing data for use in setting, modifying, and storing the internal functions; and an execution state stack unit for storing data indicating the state of the internal functions being executed. The data processing apparatus includes an internal resource management unit for setting and modifying the internal functions, and saving and restoring, through the execution state stack unit, the data indicating the state of the functions being executed. This system allows the processes to be freely performed by the device and the data processing apparatus at a high speed.

Abstract: A decoder to decode input data which includes an instruction code. The decoder includes a high-order address generator which uses the instruction code in the generation of the high-order address, and a storage circuit which stores control codes that corresponded to the instruction code. Indication data is stored in the beginning or end of the storage area to indicate the number of control codes present in the storage area. The address generated by the high-order address generator locates the desired control codes. A low-order address generator uses the indication data to count the number of control codes and derive a low-order address offset from the high order address. An internal address generator generates an internal address from a combination of the high-order and low-order addresses. The internal address is supplied to the storage circuit serially read out the control codes as the internal address is continuously incremented.

Abstract: An electron beam exposure system includes a pattern memory for storing bitmap data of a pattern to be exposed, wherein the pattern memory includes a number of latch elements arranged in rows and columns such that the writing of the bitmap data is achieved line by line and such that the reading of the bitmap data is achieved column by column.

Abstract: A charged particle beam-exposure method in which a subject is exposed to a pattern via a charged particle beam having an on/off exposure characteristic. A blanking aperture array has n open/close devices which individually/correspond to respective scan positions of the charged particle beam and operate to control the on/off exposure characteristic of the charged particle beam.

Abstract: A blanking aperture array for use in a charged particle beam exposure has a substrate, at least m rows by n columns of apertures arranged two-dimensionally in the substrate, where each of the apertures have a pair of blanking electrodes and m and n are integers greater than one, and n m-bit shift registers provided on the substrate for applying voltages dependent on pattern data to m pairs of the blanking electrodes of the apertures in the ith column, where i=1, 2, . . . , n. The pattern data is related to a pattern which is to be exposed using the blanking aperture array.

Abstract: A charged particle beam exposure system is directed to an exposure process of an electron beam for sequentially scanning an electron beam employing a blanking aperture array including a plurality of blanking apertures. The system facilitates re-focusing for compensation of focus error due to Coulumb effect and makes wiring the blanking aperture array easier. The system further allows exposure without an irradiation gap. The blanking aperture array 6 is formed with a plurality of said blanking apertures 62 arranged in a two-dimensional configuration. A control system 24 controls the blanking aperture array 62 to set the blanking aperture to the ON state where the charged particle beams pass through the blanking aperture and reach the object 19 to be exposed or the OFF state where the charged particle beams cannot reach the object 19 to be exposed.

Abstract: An electron beam exposure system comprises a pattern data generator for producing first pattern data indicative of a desired pattern of electron beam to be written on a wafer and second pattern data indicative of the number of repetitions of the pattern specified by the first pattern data, as a time sequential mixture of the first and second pattern data. The time sequential mixture of the data is sorted in a data sorting unit into a parallel data of the first pattern data and the second pattern data. Then, a discrimination is made whether the data is the first pattern data or the second pattern data, and when the data is the second pattern data, the data that follows immediately behind the second pattern data is transferred to an output path simultaneously with the second pattern data, which is transferred to another output path. Thereby, the first and second pattern data form a parallel data.

Abstract: A blanking aperture array for use in a charged particle beam exposure has a substrate, at least m rows by n columns of apertures arranged two-dimensionally in the substrate, where each of the apertures have a pair of blanking electrodes and m and n are integers greater than one, and n m-bit shift registers provided on the substrate for applying voltages dependent on pattern data to m pairs of the blanking electrodes of the apertures in the ith column, where i=1, 2, . . . , n. The pattern data is relates to a pattern which is to be exposed using the blanking aperture array.

Abstract: A charged-particle beam exposure method which has a stencil mask formed with a several mask patterns, deflects a beam of charged particles to a mask pattern selected from among the several mask patterns and shapes the beam, and performs wafer exposure by deflecting the shaped beam and illuminating the same onto a wafer.

Abstract: An electron beam exposure system comprises a beam source for producing an electron beam, a focusing unit for focusing the electron beam on the object, a first deflector for deflecting the electron beam over a first area, a second deflector for deflecting the electron beam over a second, smaller area, and a control unit for controlling the first and second deflectors by first and second deflector signals. The control unit includes a data control device for producing first address data in response to pattern data, a first memory for storing, in each address, the first deflection data and second, corresponding address data, a second memory for storing, in each address, the second deflection data, and a decoding unit supplied with the first and second deflection data for producing the first and second deflection control signals for controlling the first and second deflectors.

Abstract: A system for aligning a mask and a semiconductor wafer comprises radiation source for producing a radiation beam, a dual focus linear Fresnel zone plate provided on the mask for focusing the radiation beam incident thereto on a surface of the semiconductor wafer which comprises a first part having a first focal length and a second part having a second focal length substantially smaller than the first focal length, a diffraction grating provided on the surface of the semiconductor wafer in correspondence to the dual focus linear Fresnel zone plate for diffracting the radiation beam focused thereon, a detector held with a predetermined relationship with respect to the radiation source and the mask for detecting the diffracted beam, a movable stage for supporting the semiconductor wafer, and a controller for moving the stage means responsive to an output signal of the detection means.

Abstract: A system for aligning a mask and a semiconductor wafer comprises radiation source for producing a radiation beam, a dual focus linear Fresnel zone plate provided on the mask for focusing the radiation beam incident thereto on a surface of the semiconductor wafer which comprises a first part having a first focal length and a second part having a second focal length substantially smaller than the first focal length, a diffraction grating provided on the surface of the semiconductor wafer in correspondence to the dual focus linear Fresnel zone plate for diffracting the radiation beam focused thereon, a detector held with a predetermined relationship with respect to the radiation source and the mask for detecting the diffracted beam, a movable stage for supporting the semiconductor wafer, and a controller for moving the stage means responsive to an output signal of the detection means.