Abstract: Disclosed herein is a display device including a display panel having a display portion configured to display an image, a plate-shaped member having a first principal surface and a second principal surface, the display panel being disposed on a second principal surface side, the plate-shaped member including a screen portion disposed in a position corresponding to the display portion, an opaque frame member disposed at a peripheral edge of the screen portion, a bonding member that has transparency and is configured to bond the display panel and the plate-shaped member to each other, a holding member disposed on the second principal surface side of the plate-shaped member, and a fixing member configured to fix the frame member and the holding member to the plate-shaped member, the plate-shaped member further including a transparent peripheral edge portion disposed on an outside of the frame member.

Abstract: Disclosed herein is a display device including a display panel having a display portion configured to display an image, a plate-shaped member having a first principal surface and a second principal surface, the display panel being disposed on a second principal surface side, the plate-shaped member including a screen portion disposed in a position corresponding to the display portion, an opaque frame member disposed at a peripheral edge of the screen portion, a bonding member that has transparency and is configured to bond the display panel and the plate-shaped member to each other, a holding member disposed on the second principal surface side of the plate-shaped member, and a fixing member configured to fix the frame member and the holding member to the plate-shaped member, the plate-shaped member further including a transparent peripheral edge portion disposed on an outside of the frame member.

Abstract: A circuit substrate module includes: a plurality of substrates which are arranged in a matrix, and on at least some of which circuit components are mounted; a plurality of first flexible substrates each of which is arranged between two adjacent substrates in a row direction among the plurality of substrates, and connects the two adjacent substrates; and a plurality of second flexible substrates each of which is arranged between two adjacent substrates in a column direction among the plurality of substrates, and connects the two adjacent substrates.

Abstract: Provided is a semiconductor device that includes: an integrated circuit (IC) chip including a terminal array that is a matrix of terminals arranged in at least seven rows and at least seven columns, the terminals including a reference terminal to which a reference voltage is applied; a capacitor electrically connected to the reference terminal; and a substrate including one main surface as a mounting surface on which the IC chip and the capacitor are mounted. The IC chip is an application specific integrated circuit (ASIC) chip or a field-programmable gate array (FPGA) chip. The reference terminal is disposed at a position within three rows or three columns from an outer edge of the terminal array.

Abstract: A mounting board includes: a first electronic component that includes first solder balls, one of the first solder balls being surrounded by at least three of the first solder balls; a first capacitor that includes a first power supply terminal and a first ground terminal; a second electronic component that includes second solder balls, each of the second solder balls not being surrounded by at least three of the second solder balls; and a second capacitor that includes a second power supply terminal and a second ground terminal. A distance from the first ground terminal to the first electronic component is less than or equal to a distance from the first power supply terminal to the first electronic component. A distance from the second power supply terminal to the second electronic component is less than or equal to a distance from the second ground terminal to the second electronic component.

Abstract: A circuit substrate module includes: a plurality of substrates which are arranged in a matrix, and on at least some of which circuit components are mounted; a plurality of first flexible substrates each of which is arranged between two adjacent substrates in a row direction among the plurality of substrates, and connects the two adjacent substrates; and a plurality of second flexible substrates each of which is arranged between two adjacent substrates in a column direction among the plurality of substrates, and connects the two adjacent substrates.

Abstract: Provided is a semiconductor device that includes: an integrated circuit (IC) chip including a terminal array that is a matrix of terminals arranged in at least seven rows and at least seven columns, the terminals including a reference terminal to which a reference voltage is applied; a capacitor electrically connected to the reference terminal; and a substrate including one main surface as a mounting surface on which the IC chip and the capacitor are mounted. The IC chip is an application specific integrated circuit (ASIC) chip or a field-programmable gate array (FPGA) chip. The reference terminal is disposed at a position within three rows or three columns from an outer edge of the terminal array.

Abstract: A mounting board includes: a first electronic component that includes first solder balls, one of the first solder balls being surrounded by at least three of the first solder balls; a first capacitor that includes a first power supply terminal and a first ground terminal; a second electronic component that includes second solder balls, each of the second solder balls not being surrounded by at least three of the second solder balls; and a second capacitor that includes a second power supply terminal and a second ground terminal. A distance from the first ground terminal to the first electronic component is less than or equal to a distance from the first power supply terminal to the first electronic component. A distance from the second power supply terminal to the second electronic component is less than or equal to a distance from the second ground terminal to the second electronic component.

Abstract: A display device includes a plurality of pixels arranged in a matrix. Each of the pixels includes a light-emitting element, a capacitance element; a drive transistor which supplies, to the light-emitting element, a current corresponding to the amount of the electric charge accumulated in the capacitance element; a first switch transistor for pre-initializing the electric charge accumulated in the capacitance element; and a second switch transistor for, after the pre-initializing, further initializing the electric charge accumulated in the capacitance element. The display device further includes: a first voltage source which outputs a first voltage (Vref2) to the capacitance element when the first switch transistor is turned on; and a second voltage source which applies a second voltage (Vref1) to the capacitance element when the second switch transistor is turned on.

Abstract: It is an object to provide a driving method of a plasma display panel, whereby a dark contrast can be improved while suppressing an erroneous discharge. In a resetting step in a first unit display period, while a first reset pulse having a predetermined peak electric potential is applied to one of first row electrodes of row electrode pairs formed in the PDP, a second reset pulse having a peak electric potential smaller than that of the first reset pulse is applied to the other of the first row electrodes. In the resetting step in a second unit display period subsequent to the first unit display period, a second reset pulse is applied to each of the one and the other of the first row electrodes.

Abstract: It is an object to provide a driving method of a plasma display panel, whereby a dark contrast can be improved while suppressing an erroneous discharge. In a resetting step in a first unit display period, while a first reset pulse having a predetermined peak electric potential is applied to one of first row electrodes of row electrode pairs formed in the PDP, a second reset pulse having a peak electric potential smaller than that of the first reset pulse is applied to the other of the first row electrodes. In the resetting step in a second unit display period subsequent to the first unit display period, a second reset pulse is applied to each of the one and the other of the first row electrodes.

Abstract: A drive method of a plasma display panel that can increase the dark contrast, without causing a discharge failure. When a discharge cell that assumes a black display state in a first field from among first and a second fields that are adjacent in time and switches to a display state representing a brightness other than black in the second field is detected as a lighting transition cell, at least one drive of the below-described first and second forced lighting drives is executed. In the first forced lighting drive, the lighting transition cell is forcibly set into the lighting mode only in the address process of a predetermined subfield within the field in the first field. In the second forced lighting drive, an adjacent discharge cell that is adjacent to the lighting transition cell is forcibly set into the lighting mode only in the address process of the predetermined subfield in the second field.

Abstract: A plasma display driving method in which, in an erase stage of a last sub-field of a one-field display period, a scanning pulse is sequentially applied to one row electrode of each of the row electrode pairs for each scanning line or for each scanning line group having a plurality of scanning lines, while an erase pulse is applied to column electrodes simultaneously with the application of the scanning pulse, to cause an erase discharge between the one row electrode and each of the column electrodes to which the erase pulse is applied.

Abstract: A method of driving a plasma display panel for avoiding an erroneous discharge. The plasma display panel has display cells formed at respective intersections of row electrode pairs and a column electrode, wherein one field of a video signal is comprised of a plurality of sub-fields, and a reset period is provided prior to an addressing period of a starting sub-field. The method has a light emission load state detection stage for detecting a light emission load state of the plasma display panel according to the video signal in the preceding field, and a first stage in the reset period for applying the first row electrodes with a pulse of a first polarity which has an applied voltage value increased over time to reach a predetermined target potential, wherein the first stage includes controlling the target potential of the first polarity pulse according to the light emission load state.

Abstract: Each of the red, green and blue phosphor layers includes magnesium oxide including a magnesium oxide crystal body having properties of causing a cathode-luminescence emission having a peak within a wavelength range of 200 nm to 300 nm upon excitation by electron beams, as a secondary electron emission.

Abstract: A plasma display panel and a drive method therefor, which can enhance a representation capability when displaying a dark image. The plasma display panel includes fluorophor layers containing magnesium oxide. The drive method includes a reset step to initialize all the pixel cells into states of one of a light-up mode and a light-off mode, and an address step in which the pixel cells are caused to perform address discharges selectively in accordance with pixel data, which are successively executed in each of a head subfield and a second subfield within a one-field display period. In reset step, a voltage that sets row electrodes on one side, in the row electrode pairs as an anode and sets the column electrodes set as a cathode is applied between the row electrodes on the one side and the column electrodes.

Abstract: A plasma display panel and a drive method therefor, which can enhance a representation capability when displaying a dark image. The plasma display panel includes fluorophor layers containing magnesium oxide. The drive method includes a reset step to initialize all the pixel cells into states of one of a light-up mode and a light-off mode, and an address step in which the pixel cells are caused to perform address discharges selectively in accordance with pixel data, which are successively executed in each of a head subfield and a second subfield within a one-field display period. In reset step, a voltage that sets row electrodes on one side, in the row electrode pairs as an anode and sets the column electrodes set as a cathode is applied between the row electrodes on the one side and the column electrodes.

Abstract: A plasma display panel and a drive method therefor, which can enhance a representation capability when displaying a dark image. The plasma display panel includes fluorophor layers containing magnesium oxide. The drive method includes a reset step to initialize all the pixel cells into states of one of a light-up mode and a light-off mode, and an address step in which the pixel cells are caused to perform address discharges selectively in accordance with pixel data, which are successively executed in each of a head subfield and a second subfield within a one-field display period. In reset step, a voltage that sets row electrodes on one side, in the row electrode pairs as an anode and sets the column electrodes set as a cathode is applied between the row electrodes on the one side and the column electrodes.

Abstract: A plasma display panel and a drive method therefor, which can enhance a representation capability when displaying a dark image. The plasma display panel includes fluorophor layers containing magnesium oxide. The drive method includes a reset step to initialize all the pixel cells into states of one of a light-up mode and a light-off mode, and an address step in which the pixel cells are caused to perform address discharges selectively in accordance with pixel data, which are successively executed in each of a head subfield and a second subfield within a one-field display period. In reset step, a voltage that sets row electrodes on one side, in the row electrode pairs as an anode and sets the column electrodes set as a cathode is applied between the row electrodes on the one side and the column electrodes.

Abstract: A plasma display panel driving method in which a reset step and an address step are sequentially executed in the first subfield and second subfield of each field. A microemission step is executed in the first subfield for generating a microemission discharge between ones of the row electrodes and the column electrodes in display cells in the ON mode by applying a voltage for using the ones of the row electrodes as the anode and the column electrodes as the cathode, between the electrodes immediately after the address step. Moreover, in the microemission step, a potential lower than the voltage generated when applying a sustain pulse is respectively applied to the ones and the others of the row electrodes while applying a voltage as described above between the ones of the row electrodes and the column electrodes.