Abstract: After P+ ions are implanted into a polysilicon film in an nMOSFET region, a heat treatment is performed to diffuse phosphorus down to the lower part of the polysilicon film. The diffusion reduces the concentration of phosphorus in an upper end portion of the polysilicon film and inhibits the upper end edges of a gate electrode from being increased in size during patterning. Then, B+ ions are implanted into the polysilicon film in a pMOSFET region and the polysilicon film is etched into a gate configuration. Since a heat treatment for simultaneously diffusing phosphorus and boron in the polysilicon film is not performed, the entrance of boron from the gate electrode into a semiconductor substrate is inhibited, while the occurrence of side etching during the formation of an n-type polysilicon gate is suppressed.

Abstract: After an organic bottom anti-reflective coating (12) is deposited on an underlying film (11), a resist pattern (15) is formed on the organic bottom anti-reflective coating (12). Dry etching is performed with respect to the organic bottom anti-reflective coating (12) masked with the resist pattern (15) to form an anti-reflective coating pattern. The dry-etching of the organic bottom anti-reflective coating (12) is performed by using etching gas containing gas having the S component such as SO2/O2-based etching gas or COS/O2-based etching gas.

Abstract: A semiconductor substrate which is placed on a bottom electrode inside a chamber is dry-etched by creating plasma inside the chamber. By making the average surface roughness Ra of the bottom surface of a quartz-top plate placed on the bottom electrode be in a range of 0.2 to 5 .mu.m, adhesion between the quartz-top plate and the deposits caused by the dry etching is enhanced, and the number of particles suspended in the chamber is reduced. Furthermore, the function of enhancing the adhesion of deposits can be maintained even after cleaning of the quartz-top plate. As a result, the number of particles which adhere onto the semiconductor substrate is reduced and the semiconductor substrate can be processed in an extremely clean atmosphere.

Abstract: Formed in a second interlayer dielectric are a first contact hole and a second contact hole. The first and second contact holes each extend to a first-level interconnect line. Tungsten is formed on the entirety of a substrate to form a first plug, a second plug, and a tungsten layer. A silicon oxide layer is formed. Thereafter, a patterning process is carried out to form a second-level interconnect line which is connected with the first plug and a top protective layer, and the top of the second plug remains exposed. A sidewall is formed on the side surfaces of the second-level interconnect line and the top protective layer. Subsequently, a third-level interconnect line, which is connected with the exposed second plug, is formed. Such arrangement not only reduces the number of contact hole formation masks, it also cuts down the number of fabrication steps. Further, the aspect ratio of the second contact hole becomes lower thereby achieving highly reliable semiconductor devices.