Patents by Inventor Shunsuke Kurachi

Shunsuke Kurachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11688773
    Abstract: Disclosure is a method for manufacturing a semiconductor device. The method includes forming a source electrode and a drain electrode on a nitride semiconductor layer formed on a main surface of a SiC substrate, forming a gate electrode having a laminated structure including a Ni layer and an Au layer on the Ni layer between the source electrode and the drain electrode on the nitride semiconductor layer and forming a first metal film having the same laminated structure as the gate electrode in a region adjacent to the source electrode with an interval therebetween, forming a second metal film to contact with the source electrode and the first metal film, forming a hole being continuous with the first metal film from a back surface of the SiC substrate, and forming a metal via being continuous with the first metal film from the back surface in the hole.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: June 27, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Shunsuke Kurachi, Tsutomu Komatani
  • Patent number: 11515208
    Abstract: A semiconductor device that comprises a substrate with a primary surface and a secondary surface opposite to the primary surface. The primary surface provides a semiconductor active device. The semiconductor device includes a base metal layer deposited on the secondary surface and within the substrate via in which a vacancy is formed, and an additional metal layer on the base metal layer, the additional metal layer having different wettability against a solder as compared to the base metal layer whereby the solder is contactable by the base metal layer and repelled by the additional metal layer. The semiconductor device is die-bonded on the assembly substrate by interposing the solder between the secondary surface and the assembly substrate. The base metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the additional metal layer is in contact with the solder.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: November 29, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Toshiyuki Kosaka, Shunsuke Kurachi
  • Publication number: 20210193520
    Abstract: A semiconductor device that comprises a substrate with a primary surface and a secondary surface opposite to the primary surface. The primary surface provides a semiconductor active device. The semiconductor device includes a base metal layer deposited on the secondary surface and within the substrate via in which a vacancy is formed, and an additional metal layer on the base metal layer, the additional metal layer having different wettability against a solder as compared to the base metal layer whereby the solder is contactable by the base metal layer and repelled by the additional metal layer. The semiconductor device is die-bonded on the assembly substrate by interposing the solder between the secondary surface and the assembly substrate. The base metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the additional metal layer is in contact with the solder.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 24, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Toshiyuki KOSAKA, Shunsuke KURACHI
  • Patent number: 10957591
    Abstract: A process of forming a semiconductor device is disclosed, where the semiconductor device provides a substrate. The process includes steps of: (a) depositing a first metal layer containing nickel (Ni) on a secondary surface of the substrate and within a substrate via provided in the substrate; (b) depositing a second metal layer on the first metal layer by electrolytic plating; (c) depositing a third metal layer on the second metal layer, where the third metal layer contains at least one of Ni and titanium (Ti); (d) exposing the second metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the third metal layer; and (e) die-bonding the semiconductor device on an assembly substrate by interposing solder between the secondary surface of the substrate and the assembly substrate.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 23, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Toshiyuki Kosaka, Shunsuke Kurachi
  • Publication number: 20200266275
    Abstract: Disclosure is a method for manufacturing a semiconductor device. The method includes forming a source electrode and a drain electrode on a nitride semiconductor layer formed on a main surface of a SiC substrate, forming a gate electrode having a laminated structure including a Ni layer and an Au layer on the Ni layer between the source electrode and the drain electrode on the nitride semiconductor layer and forming a first metal film having the same laminated structure as the gate electrode in a region adjacent to the source electrode with an interval therebetween, forming a second metal film to contact with the source electrode and the first metal film, forming a hole being continuous with the first metal film from a back surface of the SiC substrate, and forming a metal via being continuous with the first metal film from the back surface in the hole.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 20, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Shunsuke KURACHI, Tsutomu Komatani
  • Publication number: 20190259662
    Abstract: A process of forming a semiconductor device is disclosed, where the semiconductor device provides a substrate. The process includes steps of: (a) depositing a first metal layer containing nickel (Ni) in the secondary surface of the substrate and within the substrate via provided in the substrate; (b) depositing a second metal layer on the first metal layer by electrolytic plating; (c) depositing a third metal layer on the second metal layer, where the third metal layer contains at least one of Ni and titanium (Ti); (d) exposing the second metal layer in a portion except for the substrate via and a periphery of the substrate via by partly removing the third metal layer; and (e) die-bonding the semiconductor device on an assembly substrate by interposing solder between the secondary surface of the substrate and the assembly substrate.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 22, 2019
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Toshiyuki KOSAKA, Shunsuke KURACHI
  • Patent number: 8952491
    Abstract: A capacitive element includes: an upper electrode; a lower electrode; and a dielectric layer that is disposed between the upper electrode and the lower electrode, and includes a first film, a second film and a third film which are made of any one of silicon nitride and aluminum oxide and laminated from a side of the lower electrode in order, a composition ratio of any one of silicon and aluminum in each of the first film and the third film being larger than a corresponding composition ratio in the second film.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: February 10, 2015
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Shunsuke Kurachi
  • Patent number: 8921950
    Abstract: A semiconductor device includes a gate electrode formed on a nitride semiconductor layer, and a source electrode and a drain electrode provided on the nitride semiconductor layer so as to interpose the gate electrode therebetween, a first silicon nitride film that covers the gate electrode and the silicon nitride film and has a composition ratio of silicon to nitrogen equal to or larger than 0.75, the first silicon nitride film having compressive stress solely, and a second silicon nitride film that is formed on the first silicon nitride film and has a composition ratio of silicon to nitrogen equal to or larger than 0.75 solely, a whole stacked layer structure of the first and second silicon nitride films having tensile stress.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: December 30, 2014
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Tsutomu Komatani, Shunsuke Kurachi
  • Publication number: 20130256755
    Abstract: A semiconductor device includes: a gate electrode that is provided on a semiconductor layer, and contains a Ni-containing layer; an insulating film that covers the gate electrode, and has a step; a covering layer that is provided between the gate electrode and the insulating film, and is arty one of a metal which has a melting point equal to or more than 1,600 degrees, and an oxide and a nitride of the metal; and a metal layer that is provided on the step.
    Type: Application
    Filed: March 26, 2013
    Publication date: October 3, 2013
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Shunsuke Kurachi
  • Patent number: 8178900
    Abstract: A semiconductor device includes a GaN-based semiconductor layer formed on a substrate, and an insulating film composed of any one of silicon nitride in which the composition ratio of silicon to nitrogen is 0.85 to 3.0, silicon oxide in which the composition ratio of silicon to oxygen is 0.6 to 3.0, or silicon oxide nitride in which the composition ratio of silicon to nitrogen and oxygen is 0.6 to 3.0 that is formed on a surface of the GaN-based semiconductor layer, a gate electrode formed on the GaN-based semiconductor layer, and a source electrode and a drain electrode formed with the gate electrode therebetween.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: May 15, 2012
    Assignee: Eudyna Devices Inc.
    Inventors: Shunsuke Kurachi, Tsutomu Komatani
  • Patent number: 7442999
    Abstract: A semiconductor substrate includes: a semiconductor crystal layer grown on one face of a substrate; and a stress relaxation layer, which is formed on the other face opposite to the one face and the side face of the substrate and applies stress to the substrate in the same direction as the direction of stress which the semiconductor crystal layer applies to the substrate. In this case, stress of the semiconductor crystal layer to the substrate is offset. Therefore, warp of the semiconductor substrate and generation of cracks are inhibited.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: October 28, 2008
    Assignee: Eudyna Devices In.
    Inventors: Shunsuke Kurachi, Tsutomu Komatani
  • Publication number: 20060220192
    Abstract: A semiconductor substrate includes: a semiconductor crystal layer grown on one face of a substrate; and a stress relaxation layer, which is formed on the other face opposite to the one face and the side face of the substrate and applies stress to the substrate in the same direction as the direction of stress which the semiconductor crystal layer applies to the substrate. In this case, stress of the semiconductor crystal layer to the substrate is offset. Therefore, warp of the semiconductor substrate and generation of cracks are inhibited.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 5, 2006
    Applicant: EUDYNA DEVICES INC.
    Inventors: Shunsuke Kurachi, Tsutomu Komatani
  • Publication number: 20060220063
    Abstract: A semiconductor device includes a GaN-based semiconductor layer formed on a substrate, and an insulating film composed of any one of silicon nitride in which the composition ratio of silicon to nitrogen is 0.85 to 3.0, silicon oxide in which the composition ratio of silicon to oxygen is 0.6 to 3.0, or silicon oxide nitride in which the composition ratio of silicon to nitrogen and oxygen is 0.6 to 3.0 that is formed on a surface of the GaN-based semiconductor layer, a gate electrode formed on the GaN-based semiconductor layer, and a source electrode and a drain electrode formed with the gate electrode therebetween.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Applicant: EUDYNA DEVICES INC.
    Inventors: Shunsuke Kurachi, Tsutomu Komatani