Patents by Inventor Shunsuke Sakamoto
Shunsuke Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11322586Abstract: A semiconductor device capable of suppressing the calorific value at the central portion of a wire bonding area is provided. A semiconductor device includes a plurality of IGBT cells in a cell area. An emitter electrode serves as a current path when a plurality of IGBT cells are in conductive state, and is formed to cover a plurality of IGBT cells. A wire is bonded to the emitter electrode. A dummy cell which does not perform a bipolar operation, is formed at least below a central portion of a wire bonding area which is an area at which the wire and the emitter electrode are bonded.Type: GrantFiled: November 13, 2019Date of Patent: May 3, 2022Assignee: Mitsubishi Electric CorporationInventor: Shunsuke Sakamoto
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Publication number: 20200227521Abstract: A semiconductor device capable of suppressing the calorific value at the central portion of a wire bonding area is provided. A semiconductor device includes a plurality of IGBT cells in a cell area. An emitter electrode serves as a current path when a plurality of IGBT cells are in conductive state, and is formed to cover a plurality of IGBT cells. A wire is bonded to the emitter electrode. A dummy cell which does not perform a bipolar operation, is formed at least below a central portion of a wire bonding area which is an area at which the wire and the emitter electrode are bonded.Type: ApplicationFiled: November 13, 2019Publication date: July 16, 2020Applicant: Mitsubishi Electric CorporationInventor: Shunsuke SAKAMOTO
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Publication number: 20120223336Abstract: A semiconductor device includes a semiconductor substrate including a collector layer of a first conductivity type and a drift layer of a second conductivity type in contact with said collector layer, said drift layer receiving a supply of carriers from said collector layer. The semiconductor device further includes a lattice defect formed to penetrate through said semiconductor substrate and enclose a predetermined portion of said semiconductor substrate, a sense emitter electrode formed on the top surface of said predetermined portion, and a collector electrode formed on the bottom surface of said predetermined portion.Type: ApplicationFiled: November 22, 2011Publication date: September 6, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Shunsuke SAKAMOTO
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Patent number: 8178365Abstract: A semiconductor wafer having IGBT elements and transistors formed on a surface thereof is prepared. Electron beams are emitted all over the surface of the semiconductor wafer. Recombination centers are formed in the IGBT elements and the transistors. ON voltages of the transistors are measured by a measurement device, and lifetimes defined in the IGBT elements and the transistors are recovered by a prescribed annealing treatment. When the lifetimes are recovered, a control device controls an annealing treatment amount in the annealing treatment based on the measured ON voltages of the transistors such that ON voltages of the IGBT elements are each equal to a desired ON voltage. Variations in the ON voltages of a plurality of IGBT elements obtained from the semiconductor wafer are reduced.Type: GrantFiled: January 21, 2011Date of Patent: May 15, 2012Assignee: Mitsubishi Electric CorporationInventors: Atsushi Narazaki, Yukio Matsushita, Masashi Osaka, Shunsuke Sakamoto
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Publication number: 20110244604Abstract: A semiconductor wafer having IGBT elements and transistors formed on a surface thereof is prepared. Electron beams are emitted all over the surface of the semiconductor wafer. Recombination centers are formed in the IGBT elements and the transistors. ON voltages of the transistors are measured by a measurement device, and lifetimes defined in the IGBT elements and the transistors are recovered by a prescribed annealing treatment. When the lifetimes are recovered, a control device controls an annealing treatment amount in the annealing treatment based on the measured ON voltages of the transistors such that ON voltages of the IGBT elements are each equal to a desired ON voltage. Variations in the ON voltages of a plurality of IGBT elements obtained from the semiconductor wafer are reduced.Type: ApplicationFiled: January 21, 2011Publication date: October 6, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Atsushi Narazaki, Yukio Matsushita, Masashi Osaka, Shunsuke Sakamoto
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Patent number: 7675113Abstract: A charge storage layer of first conductive type is formed on the first principal surface of a semiconductor substrate. A base layer of second conductive type is formed on the charge storage layer. Each trench formed through the base layer and the charge storage layer is lined with an insulating film and filled with a trench gate electrode. Dummy trenches are formed on both sides of each trench. Source layers of first conductive type are selectively formed in the surface of the base layer and in contact with the sidewalls of the trenches. The source layers are spaced apart from each other and arranged in the longitudinal direction of the trenches. A contact layer of second conductive type is formed in the surface of the base layer and between each two adjacent source layers arranged in the longitudinal direction of the trenches. A collector layer of second conductive type is formed on the second principal surface of the semiconductor substrate.Type: GrantFiled: August 22, 2007Date of Patent: March 9, 2010Assignee: Mitsubishi Electric CorporationInventors: Shunsuke Sakamoto, Eisuke Suekawa, Tetsujiro Tsunoda
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Publication number: 20080224207Abstract: A charge storage layer of first conductive type is formed on the first principal surface of a semiconductor substrate. A base layer of second conductive type is formed on the charge storage layer. Each trench formed through the base layer and the charge storage layer is lined with an insulating film and filled with a trench gate electrode. Dummy trenches are formed on both sides of each trench. Source layers of first conductive type are selectively formed in the surface of the base layer and in contact with the sidewalls of the trenches. The source layers are spaced apart from each other and arranged in the longitudinal direction of the trenches. A contact layer of second conductive type is formed in the surface of the base layer and between each two adjacent source layers arranged in the longitudinal direction of the trenches. A collector layer of second conductive type is formed on the second principal surface of the semiconductor substrate.Type: ApplicationFiled: August 22, 2007Publication date: September 18, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Shunsuke SAKAMOTO, Eisuke Suekawa, Tetsujiro Tsunoda