Patents by Inventor SHUNSUKE SAKAZUME

SHUNSUKE SAKAZUME has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220146647
    Abstract: A light receiving device includes: a pixel array unit that includes pixels that receive light; a first frequency generation unit; a time measurement unit that operates on the basis of a signal from the first frequency generation unit and outputs a digital code in accordance with a time difference between a timing of light emission from a light source and a timing of light reception by the pixels; a second frequency generation unit; and a selection unit that selectively supplies the time measurement unit with one of a signal from the pixels or a signal from the second frequency generation unit.
    Type: Application
    Filed: March 13, 2020
    Publication date: May 12, 2022
    Inventor: SHUNSUKE SAKAZUME
  • Publication number: 20220082669
    Abstract: A measurement apparatus (110A) according to an embodiment includes: a time-to-digital converter circuit (111) that measures a time period between an emission timing at which light is emitted from a light emitting unit (101) and a time point at which a light receiving unit (102) receives the light; a delay means (114A) that adds, to the time period measured by the time-to-digital converter circuit, a positive or a negative delay having a length that is different from a cycle of a clock used by the time-to-digital converter circuit and that is used as a unit amount of delay; and a storage unit (112) that stores therein time information that indicates the time period measured by the time-to-digital converter circuit and delay information that indicates an amount of delay to be added by the delay means, in association with each other, related to each of a case in which a delay is added by the delay means and a case in which a delay is not added by the delay means.
    Type: Application
    Filed: March 4, 2020
    Publication date: March 17, 2022
    Inventors: HIROKI HIYAMA, SHUNSUKE SAKAZUME
  • Patent number: 10523219
    Abstract: The present technology relates to a phase locked loop and a control method therefor, which are capable of achieving low power consumption and good phase noise while suppressing the growth of circuit area.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: December 31, 2019
    Assignee: SONY CORPORATION
    Inventors: Masahisa Tamura, Shunsuke Sakazume, Takeshi Matsubara, Ken Yamamoto
  • Publication number: 20190068205
    Abstract: The present technology relates to a phase locked loop and a control method therefor, which are capable of achieving low power consumption and good phase noise while suppressing the growth of circuit area.
    Type: Application
    Filed: February 20, 2017
    Publication date: February 28, 2019
    Inventors: MASAHISA TAMURA, SHUNSUKE SAKAZUME, TAKESHI MATSUBARA, KEN YAMAMOTO