Abstract: A delay circuit is disclosed. A switched-capacitor group includes a plurality of switched-capacitor units, each of which have a switching element and a capacitive element charged/discharged by turning on/off the switching element. The switched-capacitor units are connected such that the input signal is input in common to all of the switched-capacitor units and the capacitive elements are charged as well such that the capacitive elements are discharged to allow the output signal to be output from the switched-capacitor units. A switching control unit performs on/off control of the switching elements to cause the capacitive elements to be charged in sequence based on the input signal, causing the capacitive element charged last time to be discharged to allow the output signal to be output in sequence from the switched-capacitor units, and performs control of all of the switching elements to be turned off upon on/off switching of the switching elements.

Abstract: According to a preferred embodiment of the present invention, an analog memory includes a first to third memory blocks. Each of the first to third memory blocks includes a plurality of capacitive elements for storing electric charges corresponding to an input signal, an output line for transferring the electric charges, and a plurality of MOS transistors each for changing connection between the capacitive element and the output line. When a signal is outputted from the output line to a buffer circuit by sequentially connecting the capacitive element to the output line in the first memory block, all connections between the capacitive elements and the output line are disconnected in the second and third memory blocks with the output line of the first memory block and the output line of the second memory block connected.

Abstract: A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors; and a switching control unit that performs on/off control of the charging and the discharging of the MOS transistors, to cause each of the capacitive elements to be charged in sequence based on the input signal, and that, upon causing the each of the capacitive elements to be charged in sequence based on the input signal, causes the capacitive element charged last time to be discharged, to allow the output signal to be output in sequence.

Abstract: A delay circuit is disclosed. A switched-capacitor group includes a plurality of switched-capacitor units, each of which have a switching element and a capacitive element charged/discharged by turning on/off the switching element. The switched-capacitor units are connected such that the input signal is input in common to all of the switched-capacitor units and the capacitive elements are charged as well such that the capacitive elements are discharged to allow the output signal to be output from the switched-capacitor units. A switching control unit performs on/off control of the switching elements to cause the capacitive elements to be charged in sequence based on the input signal, causing the capacitive element charged last time to be discharged to allow the output signal to be output in sequence from the switched-capacitor units, and performs control of all of the switching elements to be turned off upon on/off switching of the switching elements.

Abstract: Normal operation is assured in a video signal processing circuit having an Y/C separator when a switch is made from a transmission mode in which the Y/C separator is bypassed to a separation mode in which Y/C separation is performed. When the controller (10) receives an instruction to switch from the transmission mode in which the driving of the Y/C separator (4) has been stopped to the separation mode in which the Y/C separator (4) is driven, the Y/C separator (4) is driven and the operation of the buffer memory in the Y/C separator (4) is started (S50).

Abstract: According to a preferred embodiment of the present invention, an analog memory includes a first to third memory blocks. Each of the first to third memory blocks includes a plurality of capacitive elements for storing electric charges corresponding to an input signal, an output line for transferring the electric charges, and a plurality of MOS transistors each for changing connection between the capacitive element and the output line. When a signal is outputted from the output line to a buffer circuit by sequentially connecting the capacitive element to the output line in the first memory block, all connections between the capacitive elements and the output line are disconnected in the second and third memory blocks with the output line of the first memory block and the output line of the second memory block connected.

Abstract: It is intended to provide a comparator circuit which uses a switched capacitor and has a small circuit size. An input INA is supplied to positive input terminals of comparators Com1 and Com2 through a capacitor Ca by means of a switch SW1. An input INB is supplied to a negative input terminal of the comparator Com1 through a capacitor Cb1 by means of a switch SW2, and in addition, is supplied to a negative input terminal of the comparator Com2 after being inverted through the use of a capacitor Cb2 by means of switches SW3 and SW4. Outputs from the comparators Com1 and Com2 are input to an exclusive OR circuit EXOR, which outputs a result of judgment as to whether or not the input INA is within the range extending between the positive input INB and the negative input INB.

Abstract: A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors and which is charged/discharged by turning on/off gates of the charging and the discharging MOS transistors, and wherein the plurality of switched capacitor units are connected such that the input signal is input in common to each of drains of the charging MOS transistors and such that the capacitive elements are charged as well as such that the capacitive elements are discharged to allow the output signal to be output from each of drains of the discharging MOS transistors; and a switching control unit that performs on/off control of each of gates of the charging and the discharging MOS transistors, to cause each of the