Patents by Inventor Shunsuke Takuma
Shunsuke Takuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240099014Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Shunsuke TAKUMA, Yuji TOTOKI, Seiji SHIMABUKURO, Tatsuya HINOUE, Kengo KAJIWARA, Akihiro TOBIOKA
-
Publication number: 20240072666Abstract: The control of the switches S21 to S28 of the DC/DC converter 120 includes a first mode in which all of the switches S21 to S28 of the DC/DC converter 120 are OFF and a plurality of second modes in which at least one of the switches S21 to S28 of the DC/DC converter 120 is ON, and when switching from the first mode to one of the plurality of second modes, a dead time Td is not provided between the first mode and the one of the plurality of second modes.Type: ApplicationFiled: July 12, 2023Publication date: February 29, 2024Applicant: Yazaki CorporationInventors: Noritaka TAGUCHI, Ryo GONDO, Daisuke MAEZAKI, Yoshiya OHNUMA, Shunsuke TAKUMA, Shohei KOMEDA
-
Patent number: 11844222Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.Type: GrantFiled: January 12, 2021Date of Patent: December 12, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Shunsuke Takuma, Yuji Totoki, Seiji Shimabukuro, Tatsuya Hinoue, Kengo Kajiwara, Akihiro Tobioka
-
Patent number: 11792986Abstract: A vertical repetition of a unit layer stack includes an insulating layer, a first sacrificial material layer, another insulating layer, and a second sacrificial material layer. A memory opening is formed through the vertical repetition, and a memory opening fill structure is formed in the memory opening. A backside trench is formed through the alternating stack. The first sacrificial material layers are replaced with first electrically conductive layers, and the second sacrificial material layer are replaced with second electrically conductive layers after formation of the first electrically conductive layers.Type: GrantFiled: April 19, 2021Date of Patent: October 17, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Keigo Kitazawa, Naoto Norizuki, Shunsuke Takuma
-
Publication number: 20230328981Abstract: A memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, a memory opening vertically extending through the first alternating stack and having a tapered sidewall surface at a level of one of the first electrically conductive layers, and a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel. One of the first electrically conductive layers includes a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening and has a contoured sidewall having a tapered sidewall segment that is parallel to the tapered sidewall surface of the lateral protrusion.Type: ApplicationFiled: April 7, 2022Publication date: October 12, 2023Inventors: Nobuyuki Fujimura, Shunsuke Takuma, Takashi Kudo, Satoshi Shimizu, Zhixin Cui
-
Publication number: 20230328984Abstract: A memory device includes at least one alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the at least one alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. The memory opening fill structure includes a lateral protrusion having a tapered sidewall surface; and one of the electrically conductive layers is a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening fill structure.Type: ApplicationFiled: December 1, 2022Publication date: October 12, 2023Inventors: Nobuyuki FUJIMURA, Takashi KUDO, Shunsuke TAKUMA, Satoshi SHIMIZU
-
Patent number: 11749554Abstract: A multi-wafer deposition tool includes a vacuum enclosure including a platen laterally surrounding multiple wafer stages, a spindle-blade assembly including a spindle and multiple transfer blades attached to the spindle, and a controller configured to transfer wafers between the multiple wafer stages through rotation of the multiple transfer blades around a rotation axis pasting through the spindle. A chamber clean process may be performed while the transfer blades of the spindle-blade assembly are positioned over the multiple wafer stages. Alternatively or additionally, a deposition cycle may be performed while the transfer blades of the spindle-blade assembly are positioned between neighboring pairs of the wafer stages and while a purge gas that flows out of purge gas openings into spaces between the wafer stages.Type: GrantFiled: November 5, 2020Date of Patent: September 5, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Makoto Tsutsue, Shunsuke Takuma
-
Publication number: 20230275451Abstract: A charger includes: a rectifier including input terminals, a cathode terminal and an anode terminal, wherein the input terminals are configured for connection to an AC power supply; a DC/DC converter including a first terminal, a second terminal and output terminals, the first terminal being configured to be connected to the cathode terminal of the rectifier, the second terminal being configured to be connected to the anode terminal of the rectifier, wherein the output terminals are configured for connection to a battery; and a power pulsation absorbing circuit including a first to third diodes, an inductor, a capacitor, a first switch and a second switch, wherein the DC/DC converter, the first and second switch are controlled to obtain a constant sum of a power outputted from the AC power supply and a power outputted from the capacitor during increasing a voltage outputted from the AC power supply.Type: ApplicationFiled: February 2, 2023Publication date: August 31, 2023Applicant: Yazaki CorporationInventors: Noritaka Taguchi, Ryo Gondo, Daisuke Maezaki, Yoshiya Ohnuma, Shunsuke Takuma, Shohei Komeda
-
Patent number: 11637038Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying the stepped surfaces, and pillar-shaped contact-opening assemblies located within a respective pillar-shaped volume vertically extending through the retro-stepped dielectric material portion and a region of the alternating stack that underlies the retro-stepped dielectric material portion. Some of the pillar-shaped contact-opening assemblies can include a first conductive plug that laterally contacts a cylindrical sidewall of a respective one of the electrically conductive layers and a conductive via structure that contacts a top surface of the first conductive plug.Type: GrantFiled: January 21, 2021Date of Patent: April 25, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Fumitaka Amano, Yuji Totoki, Shunsuke Takuma
-
Patent number: 11637118Abstract: A alternating stack of insulating layers and sacrificial material layers is formed over a substrate. An array of memory opening fill structures and an array of support pillar structures are formed through the alternating stack. Backside trenches are formed through the alternating stack by performing an anisotropic etch process. The anisotropic etch process etches peripheral portions of a subset of the array of support pillar structures. The sacrificial material layers are replaced with electrically conductive layer by forming backside recesses while the support pillar structures provide mechanical support to the insulating layers.Type: GrantFiled: September 29, 2020Date of Patent: April 25, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Shunsuke Takuma, Seiji Shimabukuro, Kengo Kajiwara
-
Publication number: 20220336486Abstract: A vertical repetition of a unit layer stack includes an insulating layer, a first sacrificial material layer, another insulating layer, and a second sacrificial material layer. A memory opening is formed through the vertical repetition, and a memory opening fill structure is formed in the memory opening. A backside trench is formed through the alternating stack. The first sacrificial material layers are replaced with first electrically conductive layers, and the second sacrificial material layer are replaced with second electrically conductive layers after formation of the first electrically conductive layers.Type: ApplicationFiled: April 19, 2021Publication date: October 20, 2022Inventors: Keigo KITAZAWA, Naoto NORIZUKI, Shunsuke TAKUMA
-
Publication number: 20220230917Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying the stepped surfaces, and pillar-shaped contact-opening assemblies located within a respective pillar-shaped volume vertically extending through the retro-stepped dielectric material portion and a region of the alternating stack that underlies the retro-stepped dielectric material portion. Some of the pillar-shaped contact-opening assemblies can include a first conductive plug that laterally contacts a cylindrical sidewall of a respective one of the electrically conductive layers and a conductive via structure that contacts a top surface of the first conductive plug.Type: ApplicationFiled: January 21, 2021Publication date: July 21, 2022Inventors: Fumitaka AMANO, Yuji TOTOKI, Shunsuke TAKUMA
-
Publication number: 20220223614Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.Type: ApplicationFiled: January 12, 2021Publication date: July 14, 2022Inventors: Shunsuke TAKUMA, Yuji TOTOKI, Seiji SHIMABUKURO, Tatsuya HINOUE, Kengo KAJIWARA, Akihiro TOBIOKA
-
Publication number: 20220139758Abstract: A multi-wafer deposition tool includes a vacuum enclosure including a platen laterally surrounding multiple wafer stages, a spindle-blade assembly including a spindle and multiple transfer blades attached to the spindle, and a controller configured to transfer wafers between the multiple wafer stages through rotation of the multiple transfer blades around a rotation axis pasting through the spindle. A chamber clean process may be performed while the transfer blades of the spindle-blade assembly are positioned over the multiple wafer stages. Alternatively or additionally, a deposition cycle may be performed while the transfer blades of the spindle-blade assembly are positioned between neighboring pairs of the wafer stages and while a purge gas that flows out of purge gas openings into spaces between the wafer stages.Type: ApplicationFiled: November 5, 2020Publication date: May 5, 2022Inventors: Makoto TSUTSUE, Shunsuke TAKUMA
-
Patent number: 11316437Abstract: An electronic circuit to receive input AC signals having different phases, and to control bidirectional switches corresponding to phases to generate, based on input AC signals having the phases, output AC signals having the phases and having a frequency different from a frequency of the input AC signals, the electronic circuit has reference signal circuitry to generate a reference signal having a frequency higher than the frequency of the output AC signals, and a commutation circuitry to control switching between voltage commutation and current commutation, wherein, in the voltage commutation, the commutation circuitry switches the bidirectional switches corresponding to the phases in sequence based on a voltage level of the output AC signals of the phases before and after a time point when an amplitude of the reference signal becomes a specific amplitude value, and in the current commutation, the commutation circuitry switches the bidirectional switches in parallel.Type: GrantFiled: July 31, 2020Date of Patent: April 26, 2022Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Jun-ichi Itoh, Keisuke Kusaka, Shunsuke Takuma, Koki Yamanokuchi, Shuichi Obayashi, Yasuhiro Kanekiyo
-
Publication number: 20210358936Abstract: A alternating stack of insulating layers and sacrificial material layers is formed over a substrate. An array of memory opening fill structures and an array of support pillar structures are formed through the alternating stack. Backside trenches are formed through the alternating stack by performing an anisotropic etch process. The anisotropic etch process etches peripheral portions of a subset of the array of support pillar structures. The sacrificial material layers are replaced with electrically conductive layer by forming backside recesses while the support pillar structures provide mechanical support to the insulating layers.Type: ApplicationFiled: September 29, 2020Publication date: November 18, 2021Inventors: Shunsuke TAKUMA, Seiji SHIMABUKURO, Kengo KAJIWARA
-
Patent number: 10950627Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate. Each of the alternating stacks laterally extend along a first horizontal direction, and neighboring pairs of the alternating stacks are laterally spaced apart along a horizontal direction by laterally alternating sequences of memory openings and dielectric pillar structures. Each of the memory openings contains a respective memory opening fill structure that includes a dielectric core, a first vertical semiconductor channel, a second vertical semiconductor channel, a first memory film, and a second memory film. The dielectric core contacts a pair of dielectric pillar structures among the dielectric pillar structures of the laterally alternating sequences.Type: GrantFiled: December 9, 2019Date of Patent: March 16, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Tatsuya Hinoue, Takaaki Iwai, Shunsuke Takuma
-
Publication number: 20210036625Abstract: An electronic circuit to receive input AC signals having different phases, and to control bidirectional switches corresponding to phases to generate, based on input AC signals having the phases, output AC signals having the phases and having a frequency different from a frequency of the input AC signals, the electronic circuit has reference signal circuitry to generate a reference signal having a frequency higher than the frequency of the output AC signals, and a commutation circuitry to control switching between voltage commutation and current commutation, wherein, in the voltage commutation, the commutation circuitry switches the bidirectional switches corresponding to the phases in sequence based on a voltage level of the output AC signals of the phases before and after a time point when an amplitude of the reference signal becomes a specific amplitude value, and in the current commutation, the commutation circuitry switches the bidirectional switches in parallel.Type: ApplicationFiled: July 31, 2020Publication date: February 4, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jun-ichi ITOH, Keisuke KUSAKA, Shunsuke TAKUMA, Koki YAMANOKUCHI, Shuichi OBAYASHI, Yasuhiro KANEKIYO
-
Patent number: 10468413Abstract: A method of forming a three-dimensional memory device includes forming memory stack structures vertically extending through an alternating stack of insulating layers and electrically conductive layers over a substrate, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel laterally surrounded by the memory film. The method also includes forming a stack of a first silicon nitride layer and a second silicon nitride layer over the memory stack structures, such that the first silicon nitride layer has a higher hydrogen-to-nitrogen ratio than the second silicon nitride layer, performing an anneal process at an elevated temperature to diffuse hydrogen from the first silicon nitride layer into the memory stack structures, and removing the first and second silicon nitride layers.Type: GrantFiled: April 6, 2018Date of Patent: November 5, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Shunsuke Takuma, Seiji Shimabukuro, Hirotada Tobita
-
Publication number: 20190312035Abstract: A method of forming a three-dimensional memory device includes forming memory stack structures vertically extending through an alternating stack of insulating layers and electrically conductive layers over a substrate, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel laterally surrounded by the memory film. The method also includes forming a stack of a first silicon nitride layer and a second silicon nitride layer over the memory stack structures, such that the first silicon nitride layer has a higher hydrogen-to-nitrogen ratio than the second silicon nitride layer, performing an anneal process at an elevated temperature to diffuse hydrogen from the first silicon nitride layer into the memory stack structures, and removing the first and second silicon nitride layers.Type: ApplicationFiled: April 6, 2018Publication date: October 10, 2019Inventors: Shunsuke Takuma, Seiji Shimabukuro, Hirotada Tobita