Patents by Inventor Shunsuke Yamagata

Shunsuke Yamagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240065600
    Abstract: An emotion estimating device, an emotion estimating system, and an emotion estimating method capable of estimating an emotion of a subject based on information obtained from daily activities can be provided. An emotion estimating device includes an interface that receives input of walking data of a subject measured by a measurement device and emotion data obtained by quantifying the emotion of the subject, a storage that stores the walking data and the emotion data, and an computer that obtains corresponding data in which a plurality of walking parameters included in the walking data stored in the storage are associated with the emotion data. When the interface newly receives the input of the walking data, the computer estimates the emotion of the subject from the plurality of walking parameters included in the newly received walking data, and outputs information indicating the estimated emotion of the subject.
    Type: Application
    Filed: August 28, 2023
    Publication date: February 29, 2024
    Applicant: ASICS CORPORATION
    Inventors: Toshiaki OKAMOTO, Ken KUSANO, Shunsuke YAMAGATA, Masaru ICHIKAWA, Satoru ABE
  • Patent number: 8423829
    Abstract: A debugger is operated in a host PC, and in response to operation of the debugger, first and second microprocessors execute an identical debug operation in parallel via first and second debug I/F devices. The host PC obtains internal information (dump results) from the first and second microprocessors via the first and second debug I/F devices and compares internal information (dump results) from the first and second microprocessors to perform failure analysis.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: April 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Shunsuke Yamagata, Hiroyuki Suzuki
  • Publication number: 20100191941
    Abstract: A debugger is operated in a host PC, and in response to operation of the debugger, first and second microprocessors execute an identical debug operation in parallel via first and second debug I/F devices. The host PC obtains internal information (dump results) from the first and second microprocessors via the first and second debug I/F devices and compares internal information (dump results) from the first and second microprocessors to perform failure analysis.
    Type: Application
    Filed: January 28, 2010
    Publication date: July 29, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Shunsuke YAMAGATA, Hiroyuki SUZUKI
  • Patent number: 5244288
    Abstract: A method and apparatus whereby information appearing on a CRT screen (410) is separately displayed in braille, using a braille web (100) in a loop form and made partly or wholly from a shape memory resin. The information from a CRT screen (410) is input to the web (100) by a braille printer (300) at a temperature within a range below the glass transition temperature of the resin. After the information has been read by the user, the displayed web portion is heated above the glass transition temperature by a heating roller (200) so that the web recovers its original, non-braille shape. The web is conveyed by a driving roller (210) along with the heating roller (200) and a driven roller (220) in the directions indicated by arrows in FIG. 1 for repeated use.
    Type: Grant
    Filed: June 19, 1992
    Date of Patent: September 14, 1993
    Assignee: Mitsubishi Jukogyo Kabushiki Kaisha
    Inventors: Hideji Nagaoka, Shunsuke Yamagata, Joji Ando, Kiyoshi Kawamura, Koichi Urakami, Satoru Kondo
  • Patent number: 4149652
    Abstract: The present invention provides a membrane structure for a liquid gas storage tank. The structure is characterized in that the bottom wall of the membrane comprises a number of elongated corrugated members arranged in a square-lattice pattern, and each member has a pair of spaced, parallel, longitudinally extending corrugations. Also, the members are assembled by joining one end of each corrugated member to substantially the mid-point of another corrugated member extending normal thereto, and each opening between the corrugated members is closed and made liquid tight by a thin plate.Preferably, each corrugated member is a sheet member of U-shaped cross-section, having a pair of vertical flanges of equal height, located between a pair of sheet members of L-shaped cross-section which are arranged back to back in spaced, parallel relationship, the top edges of respective adjacent vertical flanges of said L-shaped and said U-shaped members being continuously welded together.
    Type: Grant
    Filed: April 4, 1978
    Date of Patent: April 17, 1979
    Assignee: Mitsubishi Jukogyo Kabushiki Kaisha
    Inventors: Kenji Ohsaka, Koichi Hagiwara, Toshikazu Niwa, Shunsuke Yamagata