Patents by Inventor Shunta Iguchi

Shunta Iguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11863144
    Abstract: Apparatus and methods for non-invasively monitoring an oscillation signal in an effort to provide a more reliable oscillation signal. An example oscillation circuit generally includes an oscillator configured to generate an oscillation signal, the oscillator comprising an oscillator core circuit for coupling to a resonator and configured to generate the oscillation signal to enable the resonator to resonate and an adjustable current source coupled to the oscillator core circuit and configured to control an amplitude of the oscillation signal; a first automatic gain control (AGC) circuit having an input coupled to an output of the oscillator and having an output coupled to a control input of the adjustable current source; a second AGC circuit configured to replicate the first AGC circuit; and logic having a first input coupled to the output of the first AGC circuit and having a second input coupled to an output of the second AGC circuit.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: January 2, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Shunta Iguchi, Nikunj Mehta, Michael Naone Farias
  • Publication number: 20230275551
    Abstract: Apparatus and methods for non-invasively monitoring an oscillation signal in an effort to provide a more reliable oscillation signal. An example oscillation circuit generally includes an oscillator configured to generate an oscillation signal, the oscillator comprising an oscillator core circuit for coupling to a resonator and configured to generate the oscillation signal to enable the resonator to resonate and an adjustable current source coupled to the oscillator core circuit and configured to control an amplitude of the oscillation signal; a first automatic gain control (AGC) circuit having an input coupled to an output of the oscillator and having an output coupled to a control input of the adjustable current source; a second AGC circuit configured to replicate the first AGC circuit; and logic having a first input coupled to the output of the first AGC circuit and having a second input coupled to an output of the second AGC circuit.
    Type: Application
    Filed: February 28, 2022
    Publication date: August 31, 2023
    Inventors: Shunta IGUCHI, Nikunj MEHTA, Michael Naone FARIAS
  • Patent number: 11496138
    Abstract: An apparatus is disclosed for providing frequency stabilization. The apparatus includes a first supply voltage node, a second supply voltage node, an oscillator circuit coupled to the first supply voltage node, at least one clock buffer coupled to the second supply voltage node and an output of the oscillator circuit, and at least one load circuit. The at least one clock buffer is configured to selectively be in a disabled state or an enabled state to pass the clock signal to at least one client of multiple clients. The at least one load circuit includes an input coupled to the output of the oscillator circuit. The at least one load circuit also includes an output configured to be coupled to a ground. The at least one load circuit is configured to be connected to the first supply voltage node for at least a portion of time.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: November 8, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Shunta Iguchi, Xu Chi, Michael Naone Farias
  • Publication number: 20220006464
    Abstract: An apparatus is disclosed for providing frequency stabilization. The apparatus includes a first supply voltage node, a second supply voltage node, an oscillator circuit coupled to the first supply voltage node, at least one clock buffer coupled to the second supply voltage node and an output of the oscillator circuit, and at least one load circuit. The at least one clock buffer is configured to selectively be in a disabled state or an enabled state to pass the clock signal to at least one client of multiple clients. The at least one load circuit includes an input coupled to the output of the oscillator circuit. The at least one load circuit also includes an output configured to be coupled to a ground. The at least one load circuit is configured to be connected to the first supply voltage node for at least a portion of time.
    Type: Application
    Filed: July 1, 2021
    Publication date: January 6, 2022
    Inventors: Shunta Iguchi, Xu Chi, Michael Naone Farias
  • Patent number: 11181939
    Abstract: An apparatus is disclosed for implementing multi-mode oscillation circuitry with stepping control. In an example aspect, the multi-mode oscillation circuitry comprises a resonator coupled to a first oscillator and a second oscillator. The multi-mode oscillation circuitry is configured to selectively be in a first configuration with the first oscillator in an active state and the second oscillator in an inactive state or a second configuration with the first oscillator in the inactive state and the second oscillator in the active state. The apparatus also includes a step-control circuit coupled to the multi-mode oscillation circuitry. The step-control circuit is configured to cause the first oscillator to switch from the inactive state to the active state and incrementally increase a first gain of the first oscillator based on the first oscillator being in the active state to enable the multi-mode oscillation circuitry to transition from the second configuration to the first configuration.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: November 23, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Shunta Iguchi, Ilker Deligoz, Michael Naone Farias
  • Publication number: 20210124383
    Abstract: A circuit for voltage regulation and an associated method and apparatus are described. The circuit generally includes an amplifier, a pass transistor coupled to a first voltage rail node, a first switch series-coupled between an output of the amplifier and a gate of the pass transistor, and a feedback path coupled between the first voltage rail node and an input of the amplifier.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventors: Shunta IGUCHI, Michael Naone FARIAS
  • Publication number: 20200371545
    Abstract: An apparatus is disclosed for implementing multi-mode oscillation circuitry with stepping control. In an example aspect, the multi-mode oscillation circuitry comprises a resonator coupled to a first oscillator and a second oscillator. The multi-mode oscillation circuitry is configured to selectively be in a first configuration with the first oscillator in an active state and the second oscillator in an inactive state or a second configuration with the first oscillator in the inactive state and the second oscillator in the active state. The apparatus also includes a step-control circuit coupled to the multi-mode oscillation circuitry. The step-control circuit is configured to cause the first oscillator to switch from the inactive state to the active state and incrementally increase a first gain of the first oscillator based on the first oscillator being in the active state to enable the multi-mode oscillation circuitry to transition from the second configuration to the first configuration.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Inventors: Shunta Iguchi, Ilker Deligoz, Michael Naone Farias
  • Patent number: 10454665
    Abstract: An apparatus is disclosed for hybrid-controlled clock generation. In an example aspect, the apparatus includes an analog control circuit, a digital control circuit, a transistor array, an oscillator circuit, and a selection circuit. The oscillator circuit is coupled to the transistor array. The selection circuit includes a first input that is coupled to the analog control circuit, a second input that is coupled to the digital control circuit, and an output that is coupled to the transistor array. The selection circuit is configured to obtain a selection signal that is indicative of the first input coupled to the analog control circuit or the second input coupled to the digital control circuit. The selection circuit is also configured to connect, based on the selection signal, the analog control circuit or the digital control circuit to the transistor array.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 22, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shunta Iguchi, Ilker Deligoz, Michael Naone Farias
  • Publication number: 20190288829
    Abstract: An apparatus is disclosed for hybrid-controlled clock generation. In an example aspect, the apparatus includes an analog control circuit, a digital control circuit, a transistor array, an oscillator circuit, and a selection circuit. The oscillator circuit is coupled to the transistor array. The selection circuit includes a first input that is coupled to the analog control circuit, a second input that is coupled to the digital control circuit, and an output that is coupled to the transistor array. The selection circuit is configured to obtain a selection signal that is indicative of the first input coupled to the analog control circuit or the second input coupled to the digital control circuit. The selection circuit is also configured to connect, based on the selection signal, the analog control circuit or the digital control circuit to the transistor array.
    Type: Application
    Filed: March 16, 2018
    Publication date: September 19, 2019
    Inventors: Shunta Iguchi, Ilker Deligoz, Michael Naone Farias
  • Patent number: 10116261
    Abstract: According to one embodiment, an oscillator circuit includes a resonant circuit and first and second negative-resistance circuits. Each of the first and second negative-resistance circuits includes a first power-supply terminal, a second power-supply terminal, an input terminal and an output terminal. The first and second negative-resistance circuits are connected in series between a first power supply and a second power supply at the first and second power-supply terminals, and connected parallel to the resonance circuit at the input and output terminals.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 30, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shunta Iguchi, Makoto Takamiya, Takayasu Sakurai
  • Publication number: 20170201216
    Abstract: According to one embodiment, an oscillator circuit includes a resonant circuit and first and second negative-resistance circuits. Each of the first and second negative-resistance circuits includes a first power-supply terminal, a second power-supply terminal, an input terminal and an output terminal. The first and second negative-resistance circuits are connected in series between a first power supply and a second power supply at the first and second power-supply terminals, and connected parallel to the resonance circuit at the input and output terminals.
    Type: Application
    Filed: September 2, 2016
    Publication date: July 13, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shunta IGUCHI, Makoto TAKAMIYA, Takayasu SAKURAI
  • Patent number: 9407201
    Abstract: A crystal oscillator circuit includes an oscillator configured to generate a signal having an oscillation amplitude. A high-pass filter is configured to filter the output signal to generate a filtered output signal. An automatic gain control (AGC) module is configured to generate an initial gain control signal when the filtered output signal is not received by the AGC module. The high-pass filter is configured to prevent the filtered output signal from being received by the AGC module when the oscillation amplitude is substantially equal to zero. The AGC module is configured to generate a steady-state gain control signal when the filtered output signal is received by the AGC module. A gain stage is configured to provide a first amount of gain to the oscillator module based on the initial gain control signal and a second amount of gain to the oscillator module based on the steady-state gain control signal.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Shunta Iguchi