Patents by Inventor Shunta MURAI

Shunta MURAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12707707
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first region, and a second region. The second electrode is separated from the first electrode. The first region includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the first conductivity type. The fifth semiconductor region, located between the fourth semiconductor region and a portion of the third semiconductor region, has a higher first-conductivity-type impurity concentration than the third semiconductor region.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: August 11, 2026
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kazutoshi Nakamura, Shunta Murai, Daiki Yoshikawa
  • Patent number: 12707687
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, and first and second regions. The first region includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a plurality of third semiconductor regions of the first conductivity type, a gate electrode, a conductive part, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type. The gate electrode faces one of the plurality of third semiconductor regions via a gate insulating layer. The conductive part faces another one of the plurality of third semiconductor regions via an insulating layer, and is electrically connected with the second electrode. The fourth and six semiconductor regions are located on the one and the other one of the plurality of third semiconductor regions, respectively.
    Type: Grant
    Filed: October 13, 2023
    Date of Patent: August 11, 2026
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shunta Murai, Daiki Yoshikawa, Kazutoshi Nakamura
  • Publication number: 20260089990
    Abstract: A semiconductor device according to an embodiment includes a transistor region, a diode region, and a termination region surrounding the transistor region and the diode region. The transistor region includes first trenches and first conductive layers in the first trenches. The diode region includes second trenches and second conductive layers in the second trenches. The termination region includes a third trench, a first electrode pad electrically connected to the first conductive layers in at least a part of the first trench, and a second electrode pad electrically connected to a second conductive layer in a second trench closest to the third trench among the second trenches.
    Type: Application
    Filed: March 7, 2025
    Publication date: March 26, 2026
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shunta MURAI, Tomoko MATSUDAI
  • Publication number: 20240321963
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, and first and second regions. The first region includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a plurality of third semiconductor regions of the first conductivity type, a gate electrode, a conductive part, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type. The gate electrode faces one of the plurality of third semiconductor regions via a gate insulating layer. The conductive part faces another one of the plurality of third semiconductor regions via an insulating layer, and is electrically connected with the second electrode. The fourth and six semiconductor regions are located on the one and the other one of the plurality of third semiconductor regions, respectively.
    Type: Application
    Filed: October 13, 2023
    Publication date: September 26, 2024
    Inventors: Shunta MURAI, Daiki YOSHIKAWA, Kazutoshi NAKAMURA
  • Publication number: 20240321869
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first region, and a second region. The second electrode is separated from the first electrode. The first region includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the first conductivity type. The fifth semiconductor region, located between the fourth semiconductor region and a portion of the third semiconductor region, has a higher first-conductivity-type impurity concentration than the third semiconductor region.
    Type: Application
    Filed: September 7, 2023
    Publication date: September 26, 2024
    Inventors: Kazutoshi NAKAMURA, Shunta MURAI, Daiki YOSHIKAWA