Patents by Inventor Shuo-Chun Kao
Shuo-Chun Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10355655Abstract: A TIA circuit is provided that utilizes current steering to adjust the gain of a TIA of the TIA circuit. As the optical input power of the optoelectronic (OE) detector that is coupled to the input of the TIA increases, the gain of the TIA is decreased via current steering, and as the optical input power of the OE detector decreases, the gain of the TIA is increased via current steering. Utilizing current steering to adjust the gain of the TIA allows the TIA circuit to have a configuration that has reduced power consumption compared to TIA circuits that use shunt feedback TIAs. In addition the TIA circuit configuration provides reduced peaking, improved linearization and high bandwidth.Type: GrantFiled: June 29, 2017Date of Patent: July 16, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Chakravartula Nallani, Georgios Asmanis, Faouzi Chaahoub, Alfred Sargezisardrud, Tony Shuo-Chun Kao
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Publication number: 20190020320Abstract: A TIA circuit is provided that utilizes current steering to adjust the gain of a TIA of the TIA circuit. As the optical input power of the optoelectronic (OE) detector that is coupled to the input of the TIA increases, the gain of the TIA is decreased via current steering, and as the optical input power of the OE detector decreases, the gain of the TIA is increased via current steering. Utilizing current steering to adjust the gain of the TIA allows the TIA circuit to have a configuration that has reduced power consumption compared to TIA circuits that use shunt feedback TIAs. In addition the TIA circuit configuration provides reduced peaking, improved linearization and high bandwidth.Type: ApplicationFiled: June 29, 2017Publication date: January 17, 2019Inventors: Chakravartula Nallani, Georgios Asmanis, Faouzi Chaahoub, Alfred Sargezisardrud, Tony Shuo-Chun Kao
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Patent number: 9413389Abstract: An electronic device includes a transmission module communicatively coupled to a synchronizer. The transmission module is configured to transform received data for transmission, receive a first instruction from the synchronizer, based on the instruction adjust the phase of a clock signal used to time the transformation of the received data, and send the adjusted clock signal to the synchronizer. The synchronizer is configured to receive the adjusted clock signal, receive a data signal comprising a frequency and a phase of data to be transmitted, based on the adjusted clock signal and the data signal, determine a second instruction for the transmission module, and provide the second instruction to the transmission module.Type: GrantFiled: January 20, 2012Date of Patent: August 9, 2016Assignee: Fujitsu LimitedInventors: Nikola Nedovic, Shuo-Chun Kao
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Patent number: 9344071Abstract: A circuit may include a pulse generation circuit configured to receive a first clock signal with a first-clock rate and a first-clock duty cycle. The pulse generation circuit may be configured to generate, based on the first clock signal, a pulse signal with a pulse frequency and with a pulse duty cycle that is smaller than the first-clock duty cycle. The circuit may also include a sub-harmonic injection locking oscillator configured to receive the pulse signal. The sub-harmonic injection locking oscillator may be configured to output, based on the pulse signal, a second clock signal with a second-clock rate that is greater than the first-clock rate and greater than the pulse frequency.Type: GrantFiled: August 20, 2014Date of Patent: May 17, 2016Assignee: FUJITSU LIMITEDInventors: Shuo-Chun Kao, Nikola Nedovic
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Publication number: 20160056804Abstract: A circuit may include a pulse generation circuit configured to receive a first clock signal with a first-clock rate and a first-clock duty cycle. The pulse generation circuit may be configured to generate, based on the first clock signal, a pulse signal with a pulse frequency and with a pulse duty cycle that is smaller than the first-clock duty cycle. The circuit may also include a sub-harmonic injection locking oscillator configured to receive the pulse signal. The sub-harmonic injection locking oscillator may be configured to output, based on the pulse signal, a second clock signal with a second-clock rate that is greater than the first-clock rate and greater than the pulse frequency.Type: ApplicationFiled: August 20, 2014Publication date: February 25, 2016Inventors: Shuo-Chun KAO, Nikola NEDOVIC
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Patent number: 9246459Abstract: A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.Type: GrantFiled: August 1, 2014Date of Patent: January 26, 2016Assignee: Fujitsu LimitedInventors: Shuo-Chun Kao, Nikola Nedovic
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Patent number: 9203381Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.Type: GrantFiled: May 2, 2014Date of Patent: December 1, 2015Assignee: Fujitsu LimitedInventors: Shuo-Chun Kao, Nikola Nedovic
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Patent number: 9153936Abstract: An optical transmitter is disclosed. In accordance with some embodiments of the present disclosure, an optical transmitter may comprise a vertical-cavity surface-emitting laser (VCSEL) and a VCSEL driver. The VCSEL driver may comprise an input stage configured to receive a voltage signal and a low-impedance output stage comprising an input coupled to the input stage and a low-impedance output coupled to the VCSEL and configured to provide a modulated output current to the VCSEL.Type: GrantFiled: June 20, 2013Date of Patent: October 6, 2015Assignee: Fujitsu LimitedInventors: Tony Shuo-Chun Kao, Nikola Nedovic
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Patent number: 9136828Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.Type: GrantFiled: May 2, 2014Date of Patent: September 15, 2015Assignee: Fujitsu LimitedInventors: Shuo-Chun Kao, Nikola Nedovic
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Patent number: 8971447Abstract: A data signal delay system may include a delay unit and a phase interpolation unit. The delay unit may include multiple delay elements that each have an element delay. The delay unit may be configured to generate multiple delay signals by delaying a data signal using the delay elements such that each of the delay signals has a different delay. The phase interpolation unit may be coupled to the delay unit and may include a mixer. The mixer may be configured to mix two of the delay signals based on mixing weights selected for the two delay signals to generate a final delayed data signal that is the data signal delayed by a final delay. The mixing weights may be selected based on the final delay.Type: GrantFiled: October 17, 2013Date of Patent: March 3, 2015Assignee: Fujitsu LimitedInventors: Shuo-Chun Kao, Nikola Nedovic
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Publication number: 20140376582Abstract: An optical transmitter is disclosed. In accordance with some embodiments of the present disclosure, an optical transmitter may comprise a vertical-cavity surface-emitting laser (VCSEL) and a VCSEL driver. The VCSEL driver may comprise an input stage configured to receive a voltage signal and a low-impedance output stage comprising an input coupled to the input stage and a low-impedance output coupled to the VCSEL and configured to provide a modulated output current to the VCSEL.Type: ApplicationFiled: June 20, 2013Publication date: December 25, 2014Inventors: Tony Shuo-Chun Kao, Nikola Nedovic
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Publication number: 20140340148Abstract: A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.Type: ApplicationFiled: August 1, 2014Publication date: November 20, 2014Inventors: Shuo-Chun Kao, Nikola Nedovic
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Patent number: 8861560Abstract: In one embodiment, a driver circuit of a vertical-cavity surface-emitting laser (VCSEL) includes bias current sources, modulation current sources, and a switch component connected to the bias current sources at a first node and to the modulation current sources at second nodes; the switch component is configured to modulate a current from the bias and modulation current sources based on an input signal to the switch component; and the switch component is also configured to provide the modulated current to the VCSEL through a folded cascode transistor.Type: GrantFiled: November 6, 2012Date of Patent: October 14, 2014Assignee: Fujitsu LimitedInventors: Nikola Nedovic, Tony Shuo-Chun Kao
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Publication number: 20140240018Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: Fujitsu LimitedInventors: SHUO-CHUN KAO, NIKOLA NEDOVIC
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Publication number: 20140240019Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: Fujitsu LimitedInventors: SHUO-CHUN KAO, NIKOLA NEDOVIC
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Patent number: 8803609Abstract: An amplifier may include a gain stage configured to convert an input voltage signal to a current signal and to amplify the input voltage signal according to a gain. The amplifier may also include a buffer stage coupled to the gain stage at an internal node. The buffer stage may be configured to convert the current signal to an output voltage signal and to buffer the current signal from the gain stage so that a frequency bandwidth of the amplifier may be approximately maintained when the gain of the gain stage is increased.Type: GrantFiled: May 10, 2012Date of Patent: August 12, 2014Assignee: Fujitsu LimitedInventors: Shuo-Chun Kao, Scott McLeod
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Patent number: 8797098Abstract: A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.Type: GrantFiled: May 22, 2012Date of Patent: August 5, 2014Assignee: Fujitsu LimitedInventors: Shuo-Chun Kao, Nikola Nedovic
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Patent number: 8787776Abstract: An optical receiver includes a photodetector for detecting incoming optical data signals and an amplifier for providing signal gain and current to voltage conversion. The detection signal generated by the photodetector may include a distortion component caused by an operating characteristic of the photodetector. A signal compensating circuit may reconstruct the received optical data signal by effectively canceling the distortion component. For this purpose, the signal compensating circuit may include a decision feedback equalizer implemented using at least one feedback filter matched to the operating characteristic of the photodetector causing the signal distortion so as to reproduce the distortion component for cancellation. Use of a control module may also configure the optical receiver in real time to account for other operating and environmental conditions of the optical receiver.Type: GrantFiled: June 3, 2011Date of Patent: July 22, 2014Assignee: The Governing Council of the University of TorontoInventors: Anthony Chan Carusone, Tony Shuo-Chun Kao, Hemesh Yasotharan
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Patent number: 8736334Abstract: A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.Type: GrantFiled: June 13, 2012Date of Patent: May 27, 2014Assignee: Fujitsu LimitedInventors: Shuo-Chun Kao, Nikola Nedovic
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Publication number: 20140126595Abstract: In one embodiment, a driver circuit of a vertical-cavity surface-emitting laser (VCSEL) includes bias current sources, modulation current sources, and a switch component connected to the bias current sources at a first node and to the modulation current sources at second nodes; the switch component is configured to modulate a current from the bias and modulation current sources based on an input signal to the switch component; and the switch component is also configured to provide the modulated current to the VCSEL through a folded cascode transistor.Type: ApplicationFiled: November 6, 2012Publication date: May 8, 2014Inventors: Nikola Nedovic, Tony Shuo-Chun Kao