Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound semiconductor layer is formed on a first device region and a second device region of a substrate. A III-V compound barrier layer is formed on the III-V compound semiconductor layer. A lamination structure is formed on the III-V compound barrier layer. The lamination structure includes a p-type doped III-V compound layer and a first mask layer disposed thereon. A patterning process is performed to the lamination structure. A first portion of the lamination structure located above the first device region is patterned by the patterning process. A second portion of the lamination structure located above the second device region is removed by the patterning process. A thickness of the second portion of the lamination structure is greater than a thickness of the first portion of the lamination structure before the patterning process.

Abstract: A process of producing a glass includes preparing a glass material including silicates; coating a refractory material on the glass material to form a refractory glass material capable of being resistant to 500-1,200° C.; subjecting the refractory glass material to heat to be deformed; shaping the deformed refractory glass material to form a half-finished product having a curved shape by molding; and cooling the half-finished product to produce a finished product. In one embodiment, the refractory material is insulating. In another embodiment, the refractory material is conductive.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.