Abstract: An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

Abstract: A semiconductor device, includes: a first conductive type semiconductor region including a first semiconductor structure, wherein the first semiconductor structure includes one or more pairs of stack, the one or more pairs of stack respectively includes a first layer and a second layer, the first layer includes AlxGa1-xN, the second layer includes AlyGa1-yN, wherein 0?x<1, 0<y<1, x<y, wherein one of the one or more pairs of stack includes an interface region located between the first layer and the second layer adjacent to the first layer; a second conductive type semiconductor region located on the first conductive type semiconductor region; and an active region located between the first conductive type semiconductor region and the second conductive type semiconductor region; wherein the first semiconductor structure includes a first dopant having a first doping concentration with a peak value at the interface region.

Abstract: A subharmonic switching digital power amplifier system includes a power amplifier core that includes at least one power amplifier operable in a power back-off region and a power supply providing at least one operating voltage to the power amplifier. Characteristically, the power amplifier is toggled at a subharmonic component of a carrier frequency (Fc) to achieve power back-off wherein the power amplifier is operated in a voltage mode or current mode driver. Multi-subharmonics can be used to further enhance the power back-off efficiency. A switching digital power amplifier system employing phase interleaving is also provided.

Abstract: A subharmonic switching digital power amplifier system includes a power amplifier core that includes at least one power amplifier operable in a power back-off region and a power supply providing at least one operating voltage to the power amplifier. Characteristically, the power amplifier is toggled at a subharmonic component of a carrier frequency (Fc) to achieve power back-off wherein the power amplifier is operated in a voltage mode or current mode driver. Multi-subharmonics can be used to further enhance the power back-off efficiency. A switching digital power amplifier system employing phase interleaving is also provided.

Abstract: An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.

Abstract: A digital phase-locked loop includes a digital loop filter, a digitally controllable oscillator (DCO), and an injection-locked calibration-free time-to-digital converter (TDC) having a ring oscillator connected to the DCO via an input buffer that converts a sinusoidal DCO signal to a differential square wave signal provided to the ring oscillator such that ring oscillator frequency matches DCO frequency. A spur cancellation loop between the TDC and digital loop filter generates a spur cancellation signal based on an estimate of a spurious tone amplitude and phase. The spur cancellation signal is subtracted from TDC output signals prior to input to the digital loop filter. The spur cancellation loop may include a gradient descent strategy, or a feedforward strategy having a high-pass filter, integer delay chain, adaptive fractional delay, and signal averaging logic to cancel multiple internal and external spurs having frequencies that are not related to the reference clock frequency.

Abstract: An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.

Abstract: A digital phase-locked loop includes a digital loop filter, a digitally controllable oscillator (DCO), and an injection-locked calibration-free time-to-digital converter (TDC) having a ring oscillator connected to the DCO via an input buffer that converts a sinusoidal DCO signal to a differential square wave signal provided to the ring oscillator such that ring oscillator frequency matches DCO frequency. A spur cancellation loop between the TDC and digital loop filter generates a spur cancellation signal based on an estimate of a spurious tone amplitude and phase. The spur cancellation signal is subtracted from TDC output signals prior to input to the digital loop filter. The spur cancellation loop may include a gradient descent strategy, or a feedforward strategy having a high-pass filter, integer delay chain, adaptive fractional delay, and signal averaging logic to cancel multiple internal and external spurs having frequencies that are not related to the reference clock frequency.

Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.