Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

Abstract: A light-emitting device is disclosed. The light-emitting device includes a light-emitting element, a driving circuit, and a compensation unit. The driving circuit is coupled to the light-emitting element, and is configured to receive a first data signal, drive the light-emitting element, and output a sensing signal. The compensation unit is coupled to the driving circuit, and is configured to receive the sensing signal and compensate the first data signal. The compensation unit includes a first comparator circuit and a second comparator circuit. The first comparator circuit includes a first addition terminal, a first subtraction terminal, and a first output terminal. The second comparator circuit includes a second addition terminal and a second subtraction terminal. The first subtraction terminal receives the sensing signal. The first output terminal is coupled to the second addition terminal.

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

Abstract: An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

Abstract: A sanitary device for the urine glucose test includes a urine container formed on an inner wall of a main body, and a measuring module with an inner space mounted at a bottom of the urine container. Within the inner space, a lens attaches to the bottom of the urine container, a rail faces a bottom surface of the lens, and a driving module moves a light unit shooting a detection beam to a measuring surface of the lens along the rail. The measuring surface contacts urine in the urine container, and reflects the detection beam out of the bottom surface into a sensor. The sensor is electrically connected to a processor. The processor determines a urine glucose level and generates a urine glucose level data instantly from an angle of incidence of the detection beam on the measuring surface and from a beam intensity signal from the sensor.

Abstract: A compute in-memory architecture comprising multiple neurons is provided. Each neuron includes one or more storage compute cells, each of which includes a logic circuit configured to receive a multi-bit input and a weight. The weight is defined by one or more weight bits. The logic circuit is further configured to output a control voltage corresponding to logic ‘HIGH’ when XNOR operation between an input sign bit and a corresponding weight bit is 1 and a corresponding input magnitude bit is also 1. A first digital-to-analog converter is formed from a first MOSCAP group in electrical communication with the logic circuit. The first MOSCAP group includes a total number of MOSCAPs equal to input magnitude bit resolution times weight bit resolution. Characteristically, each MOSCAP in the first MOSCAP group has a first end that receives the control voltage, and a second end in electrical communication with a first summation line.

Abstract: A subharmonic switching power amplifier architecture includes a power amplifier core that includes at least one power amplifier that receives an input signal and is operable in a power back-off region. Characteristically, the at least one power amplifier is configured to be toggled at a carrier frequency (Fc) when the power level of the input signal is equal to or higher than a predetermined power level and at a subharmonic component of the carrier frequency when the power level of the input signal is less than the predetermined power level. Concurrent harmonic tuning and subharmonic tuning is implemented to enhance the efficiency at both peak power mode and power back-off mode. Characteristically, the power amplifier being configured to be operated by a voltage mode or current mode driver and in the current mode with zero-voltage-switching.

Abstract: A circuit arrangement includes an array of switches that represent a Boolean satisfiability expression that has a plurality of clauses each defined by a combination of Boolean variables Xi or ¬Xi, a first plane, and a constraints network operatively arranged with the first plane. The constraints network enforces each of the clauses such that values of different ones of the variables continue to randomly or pseudo randomly flip until the values of the variables Xi and ¬Xi stop changing or a predetermined condition occurs.

Abstract: A semiconductor device, includes: a first conductive type semiconductor region including a first semiconductor structure, wherein the first semiconductor structure includes one or more pairs of stack, the one or more pairs of stack respectively includes a first layer and a second layer, the first layer includes AlxGa1-xN, the second layer includes AlyGa1-yN, wherein 0?x<1, 0<y<1, x<y, wherein one of the one or more pairs of stack includes an interface region located between the first layer and the second layer adjacent to the first layer; a second conductive type semiconductor region located on the first conductive type semiconductor region; and an active region located between the first conductive type semiconductor region and the second conductive type semiconductor region; wherein the first semiconductor structure includes a first dopant having a first doping concentration with a peak value at the interface region.

Abstract: A subharmonic switching digital power amplifier system includes a power amplifier core that includes at least one power amplifier operable in a power back-off region and a power supply providing at least one operating voltage to the power amplifier. Characteristically, the power amplifier is toggled at a subharmonic component of a carrier frequency (Fc) to achieve power back-off wherein the power amplifier is operated in a voltage mode or current mode driver. Multi-subharmonics can be used to further enhance the power back-off efficiency. A switching digital power amplifier system employing phase interleaving is also provided.

Abstract: A subharmonic switching digital power amplifier system includes a power amplifier core that includes at least one power amplifier operable in a power back-off region and a power supply providing at least one operating voltage to the power amplifier. Characteristically, the power amplifier is toggled at a subharmonic component of a carrier frequency (Fc) to achieve power back-off wherein the power amplifier is operated in a voltage mode or current mode driver. Multi-subharmonics can be used to further enhance the power back-off efficiency. A switching digital power amplifier system employing phase interleaving is also provided.

Abstract: An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.

Abstract: A digital phase-locked loop includes a digital loop filter, a digitally controllable oscillator (DCO), and an injection-locked calibration-free time-to-digital converter (TDC) having a ring oscillator connected to the DCO via an input buffer that converts a sinusoidal DCO signal to a differential square wave signal provided to the ring oscillator such that ring oscillator frequency matches DCO frequency. A spur cancellation loop between the TDC and digital loop filter generates a spur cancellation signal based on an estimate of a spurious tone amplitude and phase. The spur cancellation signal is subtracted from TDC output signals prior to input to the digital loop filter. The spur cancellation loop may include a gradient descent strategy, or a feedforward strategy having a high-pass filter, integer delay chain, adaptive fractional delay, and signal averaging logic to cancel multiple internal and external spurs having frequencies that are not related to the reference clock frequency.

Abstract: An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.

Abstract: A digital phase-locked loop includes a digital loop filter, a digitally controllable oscillator (DCO), and an injection-locked calibration-free time-to-digital converter (TDC) having a ring oscillator connected to the DCO via an input buffer that converts a sinusoidal DCO signal to a differential square wave signal provided to the ring oscillator such that ring oscillator frequency matches DCO frequency. A spur cancellation loop between the TDC and digital loop filter generates a spur cancellation signal based on an estimate of a spurious tone amplitude and phase. The spur cancellation signal is subtracted from TDC output signals prior to input to the digital loop filter. The spur cancellation loop may include a gradient descent strategy, or a feedforward strategy having a high-pass filter, integer delay chain, adaptive fractional delay, and signal averaging logic to cancel multiple internal and external spurs having frequencies that are not related to the reference clock frequency.

Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.