Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: An audio interface circuit including a processor, an audio jack, a first filter circuit, a second filter circuit, a first clamp circuit, a second clamp circuit, a third filter circuit, and a fourth filter circuit is provided. A first clamp circuit and a second clamp circuit between a third and fourth electrodes and a processor, so that the third and fourth electrodes are allowed to be coupled to a microphone.

Abstract: An audio interface circuit including a processor, an audio jack, a first filter circuit, a second filter circuit, a first clamp circuit, a second clamp circuit, a third filter circuit, and a fourth filter circuit is provided. A first clamp circuit and a second clamp circuit between a third and fourth electrodes and a processor, so that the third and fourth electrodes are allowed to be coupled to a microphone.

Abstract: A control circuit of a power converter includes: an error detection circuit, configured to operably generate an error signal according to a reference signal and a feedback signal when coupling with an external feedback node of an external feedback circuit; an output signal detecting circuit, positioned inside the control circuit, configured to operably receive and detect an output signal of the power converter to generate a representative signal; an on time deciding circuit, coupled with the output signal detecting circuit, configured to operably generate an on time signal according to the representative signal; and a control signal generating circuit, coupled with the error detection circuit and the on time deciding circuit, configured to operably control on time of one or more power switches of the power converter according to the error signal and the on time signal.

Abstract: A control circuit of a power converter includes: an error detection circuit, configured to operably generate an error signal according to a reference signal and a feedback signal when coupling with an external feedback node of an external feedback circuit; an output signal detecting circuit, positioned inside the control circuit, configured to operably receive and detect an output signal of the power converter to generate a representative signal; an on time deciding circuit, coupled with the output signal detecting circuit, configured to operably generate an on time signal according to the representative signal; and a control signal generating circuit, coupled with the error detection circuit and the on time deciding circuit, configured to operably control on time of one or more power switches of the power converter according to the error signal and the on time signal.

Abstract: The present invention discloses a switching regulator and a control circuit thereof. The switching regulator includes a boost or buck-boost power stage, a first operation circuit and a bypass circuit. The power stage controls at least one power transistor switch included therein according to a first operation signal, to convert an input voltage to an output voltage at an output terminal. The first operation circuit generates the first operation signal in response to the output voltage or a related signal thereof. The bypass circuit includes a bypass transistor and a second operation circuit. When it is required to provide power to the output terminal promptly, the second operation circuit turns ON the bypass transistor, and when the input voltage is equal to the output voltage or equal to a sum of the output voltage plus a safety offset value, the second operation circuit turns OFF the bypass transistor.

Abstract: An underwater thruster includes a housing unit having a first opening, a cover unit connected to the housing unit and covering the first opening, a supporting unit connected to the housing unit, a motor having a driving shaft that extends through the first opening, a magnetic core unit connected to the driving shaft, a plurality of magnetic intermediate units disposed on the supporting unit and driven by the magnetic core unit, a magnetic surrounding unit driven by the magnetic intermediate units in a rotational speed smaller than the rotational speed of the magnetic core unit, and a propelling unit connected to the magnetic surrounding unit and having a plurality of angularly spaced-apart blades.