Abstract: The described techniques implement an electronic design with transistor level satisfiability models by identifying a plurality of channel connected components of an electronic design for sensitization. These techniques further determine a set of transistor level satisfiability (SAT) models for the plurality of channel connected components of the electronic design and transform the plurality of channel connected components into a set of conjunctive normal form (CNF) formulae using at least the set of transistor level SAT models. The plurality of channel connected components of the electronic design may be sensitized at least by determining one or more satisfying assignments with the set of CNF formulae. These techniques may also generate transistor level satisfiability (SAT) logic models and transistor level SAT state models for a circuit component based in part or in whole upon design specifications and one or more characteristics of the circuit component.