Abstract: This application discloses a nanoscale failure analysis method, including step 1: placing a first sample to be analyzed on a sample stage of an FIB machine, and performing cutting on a selected area of the first sample by using an ion beam in the FIB machine to form a first cross section and expose a metal pattern on the first cross section; step 2: depositing a protective layer on the first cross section by using an electron beam of the FIB machine; step 3: transferring the first sample to a nano prober, the protective layer being used for protecting the metal pattern and preventing metal diffusion in a transfer process; step 4: performing surface micro treatment on the first sample by using an ion source in the nano prober to remove the protective layer; step 5: performing probing on the metal pattern and implementing electrical testing through the nano prober.

Abstract: The present application discloses a method for locating an open circuit failure point of a test structure, which includes the following steps: step 1: providing a sample formed with a test structure, a first metal layer pattern and a second metal layer pattern of the test structure forming a series resistor structure through each via; step 2: performing a first active voltage contrast test to the sample to show an open circuit point and making a first scratch mark at an adjacent position of the open circuit point; step 3: forming a coating mark at the first scratch mark on the sample; step 4: performing a second active voltage contrast test to the sample to show the open circuit point and locating a relative position of the open circuit point by using a position of the coating mark as a reference position.

Abstract: The present application discloses a method for locating an open circuit failure point of a test structure, which includes the following steps: step 1: providing a sample formed with a test structure, a first metal layer pattern and a second metal layer pattern of the test structure forming a series resistor structure through each via; step 2: performing a first active voltage contrast test to the sample to show an open circuit point and making a first scratch mark at an adjacent position of the open circuit point; step 3: forming a coating mark at the first scratch mark on the sample; step 4: performing a second active voltage contrast test to the sample to show the open circuit point and locating a relative position of the open circuit point by using a position of the coating mark as a reference position.