Patents by Inventor Shuren Qu

Shuren Qu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250219040
    Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Tolga ACIKALIN, Soham AGARWAL, Benjamin T. DUONG, Jeremy D. ECTON, Kari E. HERNANDEZ, Brandon Christian MARIN, Pratyush MISHRA, Pratyasha MOHAPATRA, Srinivas Venkata Ramanuja PIETAMBARAM, Marcel M. SAID, Suddhasattwa NAD, Gang DUAN, Zhixin XIE, Jung Kyu HAN, Mohamed R. SABER, Shuren QU, Naiya SOETAN-DODD, Teng SUN, Yuxin FANG
  • Publication number: 20250210491
    Abstract: Integrated circuit (IC) devices and systems with embedded utility patches, and methods of forming the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a first substrate with a cavity, and one or more second substrates embedded in the cavity. The first substrate is oriented on a first plane, and the one or more second substrates are oriented on one or more second planes that are substantially orthogonal to the first plane.
    Type: Application
    Filed: December 26, 2023
    Publication date: June 26, 2025
    Applicant: Intel Corporation
    Inventors: Mohamed R. Saber, Shuren Qu, Wei-Lun Jen, Naiya Soetan-Dodd, Sheng Li
  • Publication number: 20250112175
    Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Jesse C. Jones, Yosef Kornbluth, Mitchell Page, Soham Agarwal, Fanyi Zhu, Shuren Qu, Hanyu Song, Srinivas V. Pietambaram, Yonggang Li, Bai Nie, Nicholas Haehn, Astitva Tripathi, Mohamed R. Saber, Sheng Li, Pratyush Mishra, Benjamin T. Duong, Kari Hernandez, Praveen Sreeramagiri, Yi Li, Ibrahim El Khatib, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Gang Duan, Jeremy Ecton, Suddhasattwa Nad, Haobo Chen, Robin Shea McRee, Mohammad Mamunur Rahman
  • Publication number: 20250096052
    Abstract: Microelectronic assemblies with glass cores that have undergone localized thermal healing and/or localized doping in regions adjacent to glass surface are disclosed. In one example, a microelectronic assembly includes a glass core having a first face, an opposing second face, a sidewall extending between the first face and the second face, a surface region, and a bulk region, where the surface region is a portion of the glass core that starts at a surface of the first face, the second face, or the sidewall and extends from the surface into the glass core by a total depth of up to about 50 micron, the bulk region is a portion of the glass core further away from the surface than the surface region, and a density of the surface region is higher than a density of the bulk region, e.g., at least about 5% higher or at least about 7.5% higher.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 20, 2025
    Applicant: Intel Corporation
    Inventors: Mohamed R. Saber, Hanyu Song, Fanyi Zhu, Bai Nie, Srinivas V. Pietambaram, Deniz Turan, Yonggang Li, Naiya Soetan-Dodd, Shuren Qu