Abstract: A character display control circuit comprises a selection circuit to select and output, as one of the RGB signals, one of a first voltage, a second voltage lower than the first voltage, and one or more third voltages existing between the first and second voltages; a holding circuit in which first data, consisting of a plurality of bits, for the selection circuit to select and output one of the first, second, and third voltages, is set in response to display timings of the display characters; and a selection control circuit to supply the selection circuit with selection signals for the selection circuit to select and output one of the first, second and third voltages depending on the first data, second data associated with the selection of the first voltage or the second voltage, and third data associated with the selection/unselection of the third voltages.

Abstract: A character display control circuit comprises a selection circuit to select and output, as one of the RGB signals, one of a first voltage, a second voltage lower than the first voltage, and one or more third voltages existing between the first and second voltages; a holding circuit in which first data, consisting of a plurality of bits, for the selection circuit to select and output one of the first, second, and third voltages, is set in response to display timings of the display characters; and a selection control circuit to supply the selection circuit with selection signals for the selection circuit to select and output one of the first, second and third voltages depending on the first data, second data associated with the selection of the first voltage or the second voltage, and third data associated with the selection/unselection of the third voltages.

Abstract: Control data indicating the vertical start positions of display characters is written into the locations of a video RAM determined by a common column address and a plurality of column addresses. In each horizontal synchronizing period, all control data is read in sequence from the video RAM and set in sequence in a vertical start position register. A match is found between the contents of the vertical position counter indicating the current vertical position and the contents of the vertical start position register. When they match, after the horizontal synchronizing period, the video RAM is accessed with the control data as the vertical position start address.