Abstract: A programmable delay generator produces a composite delayed pulse from an input pulse, and the leading edge of the composite delayed pulse is controlled by a voltage comparator with a variable reference voltage level supplied from a digital-to-analog converter; however, an OR gate determines the trailing edge of the composite delayed pulse with a delayed input pulse supplied from a delay circuit so that the trailing edge is independently controllable regardless of the time delay introduced by the voltage comparator.

Abstract: A latch circuit of the present invention has first and second current paths. When a reset signal of high level is supplied to the latch circuit, a current path, through which constant current is flowing, is switched from the first current path to the second current path so that an output terminal is forced to be reset.

Abstract: An emitter follower output circuit includes a first bipolar transistor for outputting a potential from its emitter to an output terminal and a second bipolar transistor, connected in series to the first bipolar transistor, for feeding a current to the first bipolar transistor. A capacitor connected between a collector of the first bipolar transistor and a base of the second bipolar transistor detects a transitional change of a potential at the collector of the first bipolar transistor and controls a potential at the base of the second bipolar transistor.