Patents by Inventor Shushi Morimoto

Shushi Morimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for manufacturing printed circuit board
    Patent number: 8276270
    Abstract: The present invention is directed to a method for manufacturing a printed circuit board in which a plurality of conductive layers forming a wiring pattern are laminated in the state where they are put between insulating layers, and a printed circuit board formed thereby. The printed circuit board manufacturing method for the present invention includes a step of forming a via fill (17) to allow electroless plating liquid to be in contact with the surface of the wiring pattern exposed to a bottom part of a via hole (14) formed at a insulating layer to laminate plating metallic film from the bottom part to a opening part of the via hole (14), to form the via fill (17), and a step of forming a wiring pattern to form electroless plating metallic film (20) serving as the wiring pattern onto a substrate where the via fill (17) is formed.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: October 2, 2012
    Assignee: C. Uyemura & Co., Ltd.
    Inventors: Teruyuki Hotta, Shushi Morimoto, Takahiro Ishizaki, Hisamitsu Yamamoto
  • METHOD FOR MANUFACTURING PRINTED CIRCUIT BOARD
    Publication number: 20100181104
    Abstract: The present invention is directed to a method for manufacturing a printed circuit board in which a plurality of conductive layers forming a wiring pattern are laminated in the state where they are put between insulating layers, and a printed circuit board formed thereby. The printed circuit board manufacturing method for the present invention includes a step of forming a via fill (17) to allow electroless plating liquid to be in contact with the surface of the wiring pattern exposed to a bottom part of a via hole (14) formed at a insulating layer to laminate plating metallic film from the bottom part to a opening part of the via hole (14), to form the via fill (17), and a step of forming a wiring pattern to form electroless plating metallic film (20) serving as the wiring pattern onto a substrate where the via fill (17) is formed.
    Type: Application
    Filed: April 22, 2008
    Publication date: July 22, 2010
    Applicant: C. UYEMURA & CO., LTD.
    Inventors: Teruyuki Hotta, Shushi Morimoto, Takahiro Ishizaki, Hisamitsu Yamamoto