Patents by Inventor Shuso Fujii

Shuso Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8310884
    Abstract: A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: November 13, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Iwai, Shuso Fujii, Shinji Miyano
  • Patent number: 8105886
    Abstract: A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: January 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuaki Otsuka, Takahiko Sasaki, Shuso Fujii
  • Publication number: 20110032778
    Abstract: A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.
    Type: Application
    Filed: March 15, 2010
    Publication date: February 10, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki Iwai, Shuso Fujii, Shinji Miyano
  • Publication number: 20080258256
    Abstract: A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.
    Type: Application
    Filed: April 8, 2008
    Publication date: October 23, 2008
    Inventors: Nobuaki Otsuka, Takahiko Sasaki, Shuso Fujii
  • Patent number: 7397686
    Abstract: A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically erasing and writing data, a control circuit configured to control the ferroelectric memory and flash EEPROM, and an interface circuit configured to communicate with the outside. The flash EEPROM stores data. The ferroelectric memory stores at least one of root information for storing the data, directory information, the file name of the data, the file size of the data, file allocation table information storing the storage location of the data, and the write completion time of the data.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: July 8, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisaburo Takashima, Shuso Fujii, Takaya Suda, Hiroshi Sukegawa
  • Patent number: 7368801
    Abstract: A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: May 6, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuaki Otsuka, Takahiko Sasaki, Shuso Fujii
  • Patent number: 7248493
    Abstract: A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit and larger than a page as a program unit. The ferroelectric memory stores a logical address-physical address conversion table using the write unit.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: July 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisaburo Takashima, Shuso Fujii, Takuya Futatsuyama, Takaya Suda, Masaki Momodomi
  • Patent number: 7218560
    Abstract: A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: May 15, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryo Fukuda, Yohji Watanabe, Shuso Fujii
  • Publication number: 20060274566
    Abstract: A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically erasing and writing data, a control circuit configured to control the ferroelectric memory and flash EEPROM, and an interface circuit configured to communicate with the outside. The flash EEPROM stores data. The ferroelectric memory stores at least one of root information for storing the data, directory information, the file name of the data, the file size of the data, file allocation table information storing the storage location of the data, and the write completion time of the data.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 7, 2006
    Inventors: Daisaburo Takashima, Shuso Fujii, Takaya Suda, Hiroshi Sukegawa
  • Publication number: 20060274565
    Abstract: A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit and larger than a page as a program unit. The ferroelectric memory stores a logical address-physical address conversion table using the write unit.
    Type: Application
    Filed: March 28, 2006
    Publication date: December 7, 2006
    Inventors: Daisaburo Takashima, Shuso Fujii, Takuya Futatsuyama, Takaya Suda, Masaki Momodomi
  • Publication number: 20060119415
    Abstract: A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.
    Type: Application
    Filed: December 5, 2005
    Publication date: June 8, 2006
    Inventors: Ryo Fukuda, Yohji Watanabe, Shuso Fujii
  • Publication number: 20050189613
    Abstract: A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.
    Type: Application
    Filed: May 24, 2004
    Publication date: September 1, 2005
    Inventors: Nobuaki Otsuka, Takahiko Sasaki, Shuso Fujii
  • Patent number: 5809225
    Abstract: A semiconductor memory includes a plurality of primary memory cells arranged in a row and column matrix formed on a semiconductor chip area and a plurality of redundant memory cells which replace primary memory cells which are found to be defective. The semiconductor memory includes a first test circuit for simultaneously writing one data value to a first number of the primary memory cells and simultaneously reading stored data from the first number of the primary memory cells to determine whether all of the stored data have the same data value, thereby performing a first parallel bit test on the first number of the primary memory cells. The first parallel bit test is performed while the semiconductor memory is in a wafer state. The semiconductor memory also includes a second test circuit which performs a second parallel bit test on a second number of primary memory cells.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: September 15, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Ohsawa, Shuso Fujii
  • Patent number: 5499211
    Abstract: A fault-tolerant DRAM design minimizes current flow in the even of a cross-fail. A bit-line precharge current limiter is provided for the bit-line precharge equalizer circuit. The bit-line precharge current limiter is both simple and effective, requiring very little silicon area to implement. The current limiter provides self current-limiting for defective bit-lines, without the necessity for a reference cell.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: March 12, 1996
    Assignees: International Business Machines Corporation, Kabushiki Kaisha Toshiba
    Inventors: Toshiaki Kirihata, Shuso Fujii, Yohji Watanabe