Abstract: A solid-state imaging device 10 includes a pixel portion 20 in which a plurality of pixels including photodiodes are arranged in rows and columns, a reading part 90 for reading pixel signals from the pixel portion, and a key generation part 82 which generates a unique key by using at least one of pixel fluctuation information or reading part fluctuation information. According to this configuration, the tamper resistance of the unique key can be secured and consequently alteration and falsification of images can be prevented.

Abstract: A solid-state imaging device 10 includes a pixel portion 20 in which a plurality of pixels including photodiodes are arranged in rows and columns, a reading part 90 for reading pixel signals from the pixel portion, and a key generation part 82 which generates a unique key by using at least one of pixel fluctuation information or reading part fluctuation information. According to this configuration, the tamper resistance of the unique key can be secured and consequently alteration and falsification of images can be prevented.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each group of adjacent pixel columns may be coupled to a respective arithmetic memory circuit via corresponding analog-to-digital converter circuitry. The arithmetic memory circuit may include at least first, second, third, and fourth arithmetic units coupled in a chain. In some arrangements, only a subset of columns in each group of adjacent pixel columns is actively coupled to the arithmetic memory circuit. In other arrangements, all of columns in each group of adjacent pixel columns are actively coupled to the arithmetic memory circuit. The columns may be directly coupled to different arithmetic units in the arithmetic memory circuit to implement weighted horizontal binning or to the same arithmetic unit in the arithmetic memory circuit to implement flat horizontal binning.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each image pixel arranged along a column may be coupled to a pixel column line. Each pixel column line may be coupled to column memory circuitry via a respective analog-to-digital converter circuit. The column memory circuitry may include multiple column memory circuits, including a spare column memory circuit. If none of the column memory circuits are defective, the spare column memory circuit is idle. If one of the column memory circuits is defective, the spare column memory circuit is engaged to bypass the defective column memory circuit. Configured in this way, the column memory circuitry is provided with column-wise memory repair capabilities.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Image pixels arranged along the same column may be coupled to a column line. The column line may be coupled to anti-eclipse control circuitry. In one suitable arrangement, the anti-eclipse control circuitry may include a data converter and an eclipse condition judgment circuit. The eclipse condition judgment circuit may be configured to record pixel output values at different points in time and to compare the recorded data to a predetermined threshold to determine whether an eclipse condition is satisfied. In another suitable arrangement, the anti-eclipse control circuitry may include a comparator and an eclipse condition judgment circuit. The comparator may compare a temporarily elevated pixel output value to a reference voltage to determine whether the eclipse condition is satisfied. In either arrangement, a maximum pixel level may be output when the eclipse condition is met.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each image pixel arranged along a column may be coupled to a pixel column line. Each pixel column line may be coupled to column memory circuitry via a respective analog-to-digital converter circuit. The column memory circuitry may include multiple column memory circuits, including a spare column memory circuit. If none of the column memory circuits are defective, the spare column memory circuit is idle. If one of the column memory circuits is defective, the spare column memory circuit is engaged to bypass the defective column memory circuit. Configured in this way, the column memory circuitry is provided with column-wise memory repair capabilities.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Image pixels arranged along the same column may be coupled to a column line. The column line may be coupled to anti-eclipse control circuitry. In one suitable arrangement, the anti-eclipse control circuitry may include a data converter and an eclipse condition judgment circuit. The eclipse condition judgment circuit may be configured to record pixel output values at different points in time and to compare the recorded data to a predetermined threshold to determine whether an eclipse condition is satisfied. In another suitable arrangement, the anti-eclipse control circuitry may include a comparator and an eclipse condition judgment circuit. The comparator may compare a temporarily elevated pixel output value to a reference voltage to determine whether the eclipse condition is satisfied. In either arrangement, a maximum pixel level may be output when the eclipse condition is met.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each group of adjacent pixel columns may be coupled to a respective arithmetic memory circuit via corresponding analog-to-digital converter circuitry. The arithmetic memory circuit may include at least first, second, third, and fourth arithmetic units coupled in a chain. In some arrangements, only a subset of columns in each group of adjacent pixel columns is actively coupled to the arithmetic memory circuit. In other arrangements, all of columns in each group of adjacent pixel columns are actively coupled to the arithmetic memory circuit. The columns may be directly coupled to different arithmetic units in the arithmetic memory circuit to implement weighted horizontal binning or to the same arithmetic unit in the arithmetic memory circuit to implement flat horizontal binning.

Abstract: Disclosed herein is a semiconductor integrated circuit including: a plurality of standard cells including a transistor having a gate electrode and arranged in combination with each other; a metallic wiring layer interconnecting the standard cells to form a desired circuit; and a plurality of reserve cells having a gate electrode, unconnected with the metallic wiring layer and arranged on a periphery of the standard cells, wherein each of the gate electrodes of the standard cells and the reserve cells has a gate pad section and two gate finger sections extending from the gate pad section to sides opposite to each other in a predetermined direction, and length of the gate pad sections of the reserve cells in a direction orthogonal to the predetermined direction is equal to or more than a sum total value of three times a minimum line width in the metallic wiring layer and twice a minimum separation distance.

Abstract: Disclosed herein is a semiconductor integrated circuit including: a plurality of standard cells including a transistor having a gate electrode and arranged in combination with each other; a metallic wiring layer interconnecting the standard cells to form a desired circuit; and a plurality of reserve cells having a gate electrode, unconnected with the metallic wiring layer and arranged on a periphery of the standard cells, wherein each of the gate electrodes of the standard cells and the reserve cells has a gate pad section and two gate finger sections extending from the gate pad section to sides opposite to each other in a predetermined direction, and length of the gate pad sections of the reserve cells in a direction orthogonal to the predetermined direction is equal to or more than a sum total value of three times a minimum line width in the metallic wiring layer and twice a minimum separation distance.

Abstract: When an operation-stop instruction is received from an RFID reader/writer, an RFID chip decodes the instruction by a control circuit and conducts the operation-stop instruction. In addition, the RFID chip uses a register which has a write-once function such as an organic memory and does not return to an original state physically if a value is written once as a register which maintains a setting whether there is an operation-stop or not.

Abstract: When an operation-stop instruction is received from an RFID reader/writer, an RFID chip decodes the instruction by a control circuit and conducts the operation-stop instruction. In addition, the RFID chip uses a register which has a write-once function such as an organic memory and does not return to an original state physically if a value is written once as a register which maintains a setting whether there is an operation-stop or not.