Patents by Inventor Shusuke Kaya
Shusuke Kaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230264007Abstract: A power supply device includes a power transmission coil which supplies electric power from outside the body in a non-contact manner via a power reception coil of an intracorporeal implanting-type medical appliance to which a drug solution is injected from outside the body. A support supports the power transmission coil, and an adhesive part is formed on the side of the support facing the body surface of a living subject.Type: ApplicationFiled: August 18, 2021Publication date: August 24, 2023Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Katsuki SUEMATSU, Atsushi HIMURA, Takeshi YAGI, Kazutaka NARA, Shusuke KAYA, Tsunenori ARAI
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Patent number: 10389239Abstract: A power conversion device converting and outputting a characteristic of input power, includes: a power conversion unit including a normally-on type first switching element made of a nitride-based semiconductor material and converting the characteristic of power by a switching operation performed by the first switching element; an operation control unit controlling a switching operation of the first switching element; and an intelligent power switch including: a second switching element provided on a power input side of the power conversion unit and turning on/off power input to the power conversion unit; and a protection control unit including a current detection unit detecting a current flowing in the second switching element and controlling on/off of the second switching element and turn off the second switching element in a case where a current detected by the current detection unit exceeds a threshold value.Type: GrantFiled: August 3, 2017Date of Patent: August 20, 2019Assignees: FURUKAWA ELECTRIC CO., LTD., FURUKAWA AUTOMOTIVE SYSTEMS INC.Inventors: Kaoru Sugimoto, Ryosuke Tamura, Shusuke Kaya, Takezo Sugimura
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Patent number: 9911842Abstract: A nitride semiconductor device includes; a semiconductor stack configured with a plurality of semiconductor layers made of nitride semiconductors provided on a base having a conductive portion; a first electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack; a second electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack separately from the first electrode; a first wiring provided at an upper layer of the first electrode; and a second wiring provided at an upper layer of the second electrode. A low permittivity area being a portion of which permittivity is lower than permittivities of the nitride semiconductors configuring the semiconductor stack at a lower layer of a portion of at least one of the first electrode and the second electrode other than a portion being junctioned with the semiconductor stack electrically.Type: GrantFiled: April 13, 2016Date of Patent: March 6, 2018Assignee: FURUKAWA ELECTRIC CO., LTD.Inventors: Kazuyuki Umeno, Shinya Otomo, Keishi Takaki, Jiang Li, Takuya Kokawa, Ryosuke Tamura, Masayuki Iwami, Shusuke Kaya, Hirotatsu Ishii
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Publication number: 20170331369Abstract: A power conversion device converting and outputting a characteristic of input power, includes: a power conversion unit including a normally-on type first switching element made of a nitride-based semiconductor material and converting the characteristic of power by a switching operation performed by the first switching element; an operation control unit controlling a switching operation of the first switching element; and an intelligent power switch including: a second switching element provided on a power input side of the power conversion unit and turning on/off power input to the power conversion unit; and a protection control unit including a current detection unit detecting a current flowing in the second switching element and controlling on/off of the second switching element and turn off the second switching element in a case where a current detected by the current detection unit exceeds a threshold value.Type: ApplicationFiled: August 3, 2017Publication date: November 16, 2017Applicants: FURUKAWA ELECTRIC CO., LTD., FURUKAWA AUTOMOTIVE SYSTEMS INC.Inventors: Kaoru SUGIMOTO, Ryosuke TAMURA, Shusuke KAYA, Takezo SUGIMURA
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Publication number: 20160225889Abstract: A nitride semiconductor device includes; a semiconductor stack configured with a plurality of semiconductor layers made of nitride semiconductors provided on a base having a conductive portion; a first electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack; a second electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack separately from the first electrode; a first wiring provided at an upper layer of the first electrode; and a second wiring provided at an upper layer of the second electrode. A low permittivity area being a portion of which permittivity is lower than permittivities of the nitride semiconductors configuring the semiconductor stack at a lower layer of a portion of at least one of the first electrode and the second electrode other than a portion being junctioned with the semiconductor stack electrically.Type: ApplicationFiled: April 13, 2016Publication date: August 4, 2016Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Kazuyuki UMENO, Shinya Otomo, Keishi Takaki, Jiang Li, Takuya Kokawa, Ryosuke Tamura, Masayuki Iwami, Shusuke Kaya, Hirotatsu Ishii
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Patent number: 8928003Abstract: The present invention prevents breakage of a gate insulating film of a MOS device and provides a nitride semiconductor device having improved reliability. An SBD metal electrode provided between a drain electrode and a gate electrode is configured to form a Schottky junction with an AlGaN layer. Further, the SBD metal electrode and a source electrode are connected and electrically short-circuited. Consequently, when an off signal is inputted to the gate electrode, a MOSFET part is turned off and the drain-side voltage of the MOSFET part becomes close to the drain electrode voltage. When the drain electrode voltage increases, the SBD metal electrode voltage becomes lower than the drain-side voltage of the MOSFET part, thus the drain side of the MOSFET part and the drain electrode are electrically disconnected by the SBD metal electrode.Type: GrantFiled: October 26, 2011Date of Patent: January 6, 2015Assignees: Furukawa Electric Co., Ltd., Fuji Electric Co., Ltd.Inventors: Katsunori Ueno, Shusuke Kaya
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Publication number: 20130292699Abstract: The present invention prevents breakage of a gate insulating film of a MOS device and provides a nitride semiconductor device having improved reliability. An SBD metal electrode provided between a drain electrode and a gate electrode is configured to form a Schottky junction with an AlGaN layer. Further, the SBD metal electrode and a source electrode are connected and electrically short-circuited. Consequently, when an off signal is inputted to the gate electrode, a MOSFET part is turned off and the drain-side voltage of the MOSFET part becomes close to the drain electrode voltage. When the drain electrode voltage increases, the SBD metal electrode voltage becomes lower than the drain-side voltage of the MOSFET part, thus the drain side of the MOSFET part and the drain electrode are electrically disconnected by the SBD metal electrode.Type: ApplicationFiled: October 26, 2011Publication date: November 7, 2013Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATIONInventors: Katsunori Ueno, Shusuke Kaya
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Patent number: 8304809Abstract: In a GaN-based semiconductor device, an active layer of a GaN-based semiconductor is formed on a silicon substrate. A trench is formed in the active layer and extends from a top surface of the active layer to a depth reaching the silicon substrate. A first electrode is formed on an internal wall surface of the trench and extends from the top surface of the active layer to the silicon substrate. A second electrode is formed on the active layer to define a current path between the first electrode and the second electrode via the active layer in an on-state of the device. A bottom electrode is formed on a bottom surface of the silicon substrate and defines a bonding pad for the first electrode. The first electrode is formed of metal in direct ohmic contact with both the silicon substrate and the active layer.Type: GrantFiled: November 13, 2008Date of Patent: November 6, 2012Assignee: Furukawa Electric Co., Ltd.Inventors: Shusuke Kaya, Seikoh Yoshida, Masatoshi Ikeda, legal representative, Sadahiro Kato, Takehiko Nomura, Nariaki Ikeda, Masayuki Iwami, Yoshihiro Sato, Hiroshi Kambayashi, Koh Li
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Patent number: 8304774Abstract: The invention provides a transistor having a leak current between a source and drain in a nitride compound semiconductor formed on a substrate that is reduced. A gate electrode, a source electrode and a drain electrode are formed respectively on the surface of the nitride compound semiconductor formed on the silicon substrate in the transistor. At least one of the source electrode and the drain electrode is surrounded by an auxiliary electrode connected with the gate electrode. Because a depletion layer is formed in the nitride compound semiconductor under the auxiliary electrode, a route of the leak current is shut off and the leak current between the source and drain may be effectively reduced.Type: GrantFiled: February 12, 2010Date of Patent: November 6, 2012Assignee: Furukawa Electric Co., Ltd.Inventors: Shusuke Kaya, Nariaki Ikeda, Jiang Li
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Publication number: 20110316048Abstract: There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode.Type: ApplicationFiled: September 2, 2011Publication date: December 29, 2011Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Nariaki Ikeda, Shusuke Kaya
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Publication number: 20110318913Abstract: There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode.Type: ApplicationFiled: September 2, 2011Publication date: December 29, 2011Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Nariaki Ikeda, Shusuke Kaya
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Patent number: 8035128Abstract: There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode.Type: GrantFiled: October 15, 2009Date of Patent: October 11, 2011Assignee: Furukawa Electric Co., Ltd.Inventors: Nariaki Ikeda, Shusuke Kaya
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Publication number: 20110198669Abstract: The invention provides a transistor having a leak current between a source and drain in a nitride compound semiconductor formed on a substrate that is reduced. A gate electrode, a source electrode and a drain electrode are formed respectively on the surface of the nitride compound semiconductor formed on the silicon substrate in the transistor. At least one of the source electrode and the drain electrode is surrounded by an auxiliary electrode connected with the gate electrode. Because a depletion layer is formed in the nitride compound semiconductor under the auxiliary electrode, a route of the leak current is shut off and the leak current between the source and drain may be effectively reduced.Type: ApplicationFiled: February 12, 2010Publication date: August 18, 2011Applicant: Furukawa Electric Co., Ltd.Inventors: Shusuke Kaya, Nariaki Ikeda, Jiang Li
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Patent number: 7943496Abstract: A method of manufacturing a GaN-based field effect transistor is provided by which a lower resistance and a higher breakdown voltage are obtained and which is less affected by a current collapse.Type: GrantFiled: February 17, 2010Date of Patent: May 17, 2011Assignee: Furukawa Electric Co., Ltd.Inventors: Takehiko Nomura, Nariaki Ikeda, Shusuke Kaya, Sadahiro Kato
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Patent number: 7812371Abstract: The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.Type: GrantFiled: March 5, 2009Date of Patent: October 12, 2010Assignee: Furukawa Electric Co., Ltd.Inventors: Shusuke Kaya, Seikoh Yoshida, Masatoshi Ikeda, legal representative, Sadahiro Kato, Takehiko Nomura, Nariaki Ikeda, Masayuki Iwami, Yoshihiro Sato, Hiroshi Kambayashi, Yuki Niiyama
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Publication number: 20100210080Abstract: A method of manufacturing a GaN-based field effect transistor is provided by which a lower resistance and a higher breakdown voltage are obtained and which is less affected by a current collapse.Type: ApplicationFiled: February 17, 2010Publication date: August 19, 2010Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Takehiko Nomura, Nariaki Ikeda, Shusuke Kaya, Sadahiro Kato
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Publication number: 20100117146Abstract: There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode.Type: ApplicationFiled: October 15, 2009Publication date: May 13, 2010Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Nariaki Ikeda, Shusuke Kaya
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Publication number: 20100117186Abstract: The invention provides a semiconductor device and a method for fabricating the same capable of preventing a field plate portion from being delaminated from an insulating film by stress inherent in a semiconductor layer even if the stress is released in forming a trench in part of the semiconductor layer where the semiconductor device is to be separated and capable of having a higher breakdown property of the semiconductor device. The semiconductor device has source, drain and gate electrodes, insulating films that insulate the electrodes on an electron supplying layer and a mesa-structure formed at part where the semiconductor device is to be separated. The gate electrode has a first electrode layer having a function of the electrode and a second electrode layer having a field plate portion whose part that contacts with the insulating film is made of a metallic material that adheres well to the insulating film.Type: ApplicationFiled: June 24, 2009Publication date: May 13, 2010Inventors: Hiroshi Kambayashi, Shusuke Kaya, Nariaki Ikeda
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Publication number: 20090278172Abstract: The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.Type: ApplicationFiled: March 5, 2009Publication date: November 12, 2009Inventors: Shusuke Kaya, Seikoh Yoshida, Sadahiro Kato, Takehiko Nomura, Nariaki Ikeda, Masayuki Iwami, Yoshihiro Sato, Hiroshi Kambayashi, Yuki Niiyama, Masatoshi Ikeda
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Publication number: 20090189191Abstract: A semiconductor device includes a field effect transistor formed of a GaN-based compound semiconductor and having a source electrode, a drain electrode, and a gate electrode, and a diode formed of a semiconductor material having a gandgap energy smaller than a bandgap energy of the GaN-based compound semiconductor. A cathode electrode and an anode electrode of the diode are electrically connected to the source electrode and the gate electrode of the field effect transistor, respectively.Type: ApplicationFiled: December 22, 2008Publication date: July 30, 2009Applicant: The Furukawa Electric Co., LTDInventors: Yoshihiro Sato, Shusuke Kaya