Patents by Inventor Shuta KOJIMA

Shuta KOJIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device
    Patent number: 11538904
    Abstract: Disclosed is a semiconductor device including a semiconductor layer having a main surface, a first conductivity type drift region formed at a surface layer part of the main surface, a super junction region having a first conductivity type first column region and a second conductivity type second column region, a second conductivity type low resistance region formed at the surface layer part of the drift region and having an impurity concentration in excess of that of the second column region, a region insulating layer formed on the main surface and covering the low resistance region such as to cause part of the low resistance region to be exposed, a first pad electrode formed on the region insulating layer such as to overlap with the low resistance region, and a second pad electrode formed on the main surface and electrically connected to the second column region and the low resistance region.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 27, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Yuto Osawa, Toshio Nakajima, Shuta Kojima
  • SEMICONDUCTOR DEVICE
    Publication number: 20210098570
    Abstract: Disclosed is a semiconductor device including a semiconductor layer having a main surface, a first conductivity type drift region formed at a surface layer part of the main surface, a super junction region having a first conductivity type first column region and a second conductivity type second column region, a second conductivity type low resistance region formed at the surface layer part of the drift region and having an impurity concentration in excess of that of the second column region, a region insulating layer formed on the main surface and covering the low resistance region such as to cause part of the low resistance region to be exposed, a first pad electrode formed on the region insulating layer such as to overlap with the low resistance region, and a second pad electrode formed on the main surface and electrically connected to the second column region and the low resistance region.
    Type: Application
    Filed: September 25, 2020
    Publication date: April 1, 2021
    Inventors: Yuto OSAWA, Toshio NAKAJIMA, Shuta KOJIMA