Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a semiconductor layer including a plurality of metal atoms on a substrate, and forming a first layer including a plurality of silicon atoms and a plurality of nitrogen atoms on the semiconductor layer. The method further includes transferring at least some of the metal atoms in the semiconductor layer into the first layer. and removing the first layer after transferring the at least some of the metal atoms in the semiconductor layer into the first layer. Furthermore, a ratio of a number of the nitrogen atoms relative to a number of the silicon atoms and the nitrogen atoms in the first layer is smaller than 4/7.

Abstract: According to one embodiment, a semiconductor memory device includes a circuitry layer, first conductive layers, a pillar layer, and a second conductive layer. The circuitry layer is provided on a substrate and includes a CMOS circuit. The first conductive layers are provided above the circuitry layer, and are stacked with an insulation layer interposed therebetween. The pillar layer crosses the first conductive layers, and includes silicon single crystal. The second conductive layer is provided on the pillar layer and includes silicon single crystal containing impurities. The first conductive layers are provided between the circuitry layer and the second conductive layer.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a semiconductor layer including a plurality of metal atoms on a substrate, and forming a first layer including a plurality of silicon atoms and a plurality of nitrogen atoms on the semiconductor layer. The method further includes transferring at least some of the metal atoms in the semiconductor layer into the first layer. and removing the first layer after transferring the at least some of the metal atoms in the semiconductor layer into the first layer. Furthermore, a ratio of a number of the nitrogen atoms relative to a number of the silicon atoms and the nitrogen atoms in the first layer is smaller than 4/7.

Abstract: A semiconductor device including a stacked body that includes insulating layers and conductive layers that are alternately stacked, a first film provided inside a recess portion that penetrates through the stacked body, a second film provided on a surface of the first film, a third film provided on a surface of the second film, and a fourth film provided on a surface of the third film. An average concentration of a halogen element per unit area in the third film and the fourth film is lower than an average concentration of the halogen element per unit area at an interface between the third film and the fourth film.

Abstract: In one embodiment, a semiconductor device includes a substrate, and a stacked film including a plurality of electrode layers and a plurality of insulating layers alternately provided above the substrate. The device further includes a first semiconductor layer provided in the stacked film, and a second semiconductor layer provided on the first semiconductor layer in the stacked film, and including a monocrystalline semiconductor layer. The device further includes an interconnect layer provided on the stacked film and the second semiconductor layer, and electrically connected to the second semiconductor layer.

Abstract: A semiconductor device including a stacked body that includes insulating layers and conductive layers that are alternately stacked, a first film provided inside a recess portion that penetrates through the stacked body, a second film provided on a surface of the first film, a third film provided on a surface of the second film, and a fourth film provided on a surface of the third film. An average concentration of a halogen element per unit area in the third film and the fourth film is lower than an average concentration of the halogen element per unit area at an interface between the third film and the fourth film.

Abstract: According to one embodiment, a semiconductor memory device includes a circuitry layer, first conductive layers, a pillar layer, and a second conductive layer. The circuitry layer is provided on a substrate and includes a CMOS circuit. The first conductive layers are provided above the circuitry layer, and are stacked with an insulation layer interposed therebetween. The pillar layer crosses the first conductive layers, and includes silicon single crystal. The second conductive layer is provided on the pillar layer and includes silicon single crystal containing impurities. The first conductive layers are provided between the circuitry layer and the second conductive layer.