Abstract: In a circuit designing method for arithmetic elements to be employed in digital signal processing, a program is produced so that a directive is added to a target arithmetic operation which provides an overflow determination about desired digital signal processing. On the basis of this program, behavioral synthesis is performed. By adding an overflow detector to the target arithmetic operation, an RTL-description circuit is produced. The operation verification of the RTL-description circuit is performed to obtain the detection results of the overflow detector. When the RTL-description circuit is again produced on the basis of the operation verification results, the output bit length of the target arithmetic operation is optimized on the basis of the overflow detection results so that overflow is suppressed, whereby an optimized RTL-description circuit can be produced.

Abstract: In the synchronous DRAM controller of this invention, when receiving a read request to an SDRAM (Synchronous Dynamic Random Access Memory) from an internal bus, a control sequencer outputs a start readout signal that synchronizes with the system clock signal. A start readout operation unit, receiving the start readout signal from the control sequencer, starts transferring a readout clock signal to the SDRAM. A signal delay path receives the readout clock signal from the start readout operation unit, delays the signal to transfer it to the SDRAM, and further delays a part of the readout clock signal to transfer it to the control sequencer. A temporary read data retention unit receives and temporarily retains a read data outputted from the SDRAM at each cycle of the readout clock signal through the signal delay path.

Abstract: In the synchronous DRAM controller of this invention, when receiving a read request to an SDRAM (Synchronous Dynamic Random Access Memory) from an internal bus, a control sequencer outputs a start readout signal that synchronizes with the system clock signal. A start readout operation unit, receiving the start readout signal from the control sequencer, starts transferring a readout clock signal to the SDRAM. A signal delay path receives the readout clock signal from the start readout operation unit, delays the signal to transfer it to the SDRAM, and further delays a part of the readout clock signal to transfer it to the control sequencer. A temporary read data retention unit receives and temporarily retains a read data outputted from the SDRAM at each cycle of the readout clock signal through the signal delay path.