Abstract: A method, apparatus and system for controlling the reading and writing of flash memories including a write control section, a plurality of read enable control signal lines and a read control section. The write control section configured to supply a write command, a write head address and first data to each of the flash memories through a bus at a predetermined timing to cause one of the flash memories to perform a write mode for writing sequentially first data from a memory address of a corresponding one of the flash memories which is accessed by the write head address in response to the write command, the write head address and first data being supplied at a predetermined timing without fetching any external signal within a first time period. The plurality of read enable control signal lines connected to the plurality of flash memories, respectively, to assign individually a plurality of read enable control signals to the flash memories via the signal lines.