Patents by Inventor Shuuichi Miura

Shuuichi Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010052901
    Abstract: A plurality of letter output devices (workstations, printers) are connected to a letter data control device by a transmission path. The control device stores letter data for transmission to the letter output devices, and is able to convert that letter data to a desired layout (e.g. from a vector font to a dot font) and then transmits the converted letter data to one or more of the letter output devices. The control device is able to select part of its stored letter data for transmission so that only commonly used letter data need be transmitted during start up of the system. Since a large amount of letter data may be stored in the control device, and only part may be transmitted to the letter output devices, those output devices can have a relatively small memory.
    Type: Application
    Filed: August 8, 2001
    Publication date: December 20, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Atsushi Kawabata, Shuuichi Miura, Kimiya Yamaashi, Yuji Taki, Yoshiki Kobayashi, Shinya Tanifuji
  • Patent number: 5600770
    Abstract: A plurality of letter output devices (workstations, printers) are connected to a letter data control device by a transmission path. The control device stores letter data for transmission to the letter output devices, and is able to convert that letter data to a desired layout (e.g. from a vector font to a dot font) and then transmits the converted letter data to one or more of the letter output devices. The control device is able to select part of its stored letter data for transmission so that only commonly used letter data need be transmitted during start up of the system. Since a large amount of letter data may be stored in the control device, and only part may be transmitted to the letter output devices, those output devices can have a relatively small memory.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: February 4, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawabata, Shuuichi Miura, Kimiya Yamaashi, Yuji Taki, Yoshiki Kobayashi, Shinya Tanifuji
  • Patent number: 5487516
    Abstract: A train control system includes an equipment for issuing, to a train under control based on a predetermined train schedule, an operational target to be attained in terms of the aimed position, aimed time and aimed speed. Once a target is issued, a possible run region of the train is determined, and another target may be set within the possible run region such that the train is not subjected to the ATC-based speed limitation or the like, thereby minimizing the cause of delay of the train operation.
    Type: Grant
    Filed: March 15, 1994
    Date of Patent: January 30, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Murata, Atsushi Kawabata, Shuuichi Miura, Korefumi Tashiro, Yasuo Morooka, Masakazu Yahiro, Masaki Katahira, Kazuo Kera
  • Patent number: 5444829
    Abstract: A plurality of letter output devices (workstations, printers) are connected to a letter data control device by a transmission path. The control device stores letter data for transmission to the letter output devices, and is able to convert that letter data to a desired layout (e.g. from a vector font to a dot font) and then transmits the converted letter data to one or more of the letter output devices. The control device is able to select part of its stored letter data for transmission so that only commonly used letter data need be transmitted during start up of the system. Since a large amount of letter data may be stored in the control device, and only part may be transmitted to the letter output devices, those output devices can have a relatively small memory.
    Type: Grant
    Filed: December 28, 1992
    Date of Patent: August 22, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawabata, Shuuichi Miura, Kimiya Yamaashi, Yuji Taki, Yoshiki Kobayashi, Shinya Tanifuji
  • Patent number: 5345560
    Abstract: A prefetch buffer adapted to be installed between a cache memory and a main memory in a computer system having a CPU. The prefetch buffer includes a buffer storage having at least one entry for storing prefetched data and an address tag, which is to be used for searching the data, as a pair; a data searcher for searching, from the data stored in the buffer storage, for data having an address requested by the CPU; and an address estimator for determining an address of data to be prefetched next from the main memory, based on the address requested by the CPU and also on a history of the addresses of data prefetched in the past from the main memory; and an address generator for generating an address of data to be prefetched from the main memory. With this arrangement, it is possible to improve the hit ratio of the prefetch buffer regardless of the direction in which the access address varies.
    Type: Grant
    Filed: July 30, 1992
    Date of Patent: September 6, 1994
    Inventors: Shuuichi Miura, Kenichi Kurosawa, Tetsuaki Nakamikawa, Kenji Hirose
  • Patent number: 5287440
    Abstract: A graphic processing device is composed of a main storage device, a drawing control device and a drawing device. The main storage device stores data relative to the coordinates of plural graphics. The drawing control device reads out the data relative to the coordinates of the plural graphics stored in the main storage device, scans the coordinate data to calculate the coordinates of intersecting points of a scanning line and the plural graphics for each position of the scanning line. The drawing control device also determines an overlapping area (AND area) or a common area (OR area) of the plural graphics on the basis of the coordinates of the intersecting points of the plural graphics and the scanning line. The drawing device draws the overlapping area (AND area) and the common area (OR area) of the plural graphics as a graphic.
    Type: Grant
    Filed: March 12, 1990
    Date of Patent: February 15, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kimiya Yamaashi, Shuuichi Miura, Yuji Taki, Atsushi Kawabata
  • Patent number: 5274717
    Abstract: An LSI parallel image processor in which line buffers and data-flow switching circuits each requiring a larger amount of hardware in the prior art are incorporated into an LSI circuit, the image data delayed by the line buffers is output from an image data output port, shift registers each having a variable number of steps for preserving local image regions are intermittently shifted-in in accordance with applied clocks, and the contents of the shift registers are sequentially read out.
    Type: Grant
    Filed: October 20, 1992
    Date of Patent: December 28, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Shuuichi Miura, Yoshiki Kobayashi, Tadashi Fukushima, Yoshiyuki Okuyama, Takeshi Katoh, Kotaro Hirasawa, Kazuyoshi Asada
  • Patent number: 4733305
    Abstract: A conversational picture processing system having a temporary memory for storing picture processing commands inputted by an operator. The system executes picture processing commands inputted by the operator, displays processed picture as a result of execution of each command, and stores the commands in the temporary memory. The system reads out a picture processing command specified by the operator from the temporary memory and stores the command as a registered command in a command list memory within the system.
    Type: Grant
    Filed: March 15, 1985
    Date of Patent: March 22, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Shuuichi Miura, Tadashi Fukushima, Yoshiki Kobayashi, Masao Takatoo, Yoichi Takagi