Patents by Inventor Shuuichi Ueno
Shuuichi Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20070190724Abstract: It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TRI) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.Type: ApplicationFiled: March 23, 2007Publication date: August 16, 2007Applicant: Renesas Technology Corp.Inventors: Yasuyoshi Itoh, Shuuichi Ueno, Haruo Furuta, Natsuo Ajika
-
Publication number: 20050169050Abstract: It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TR1) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.Type: ApplicationFiled: February 8, 2005Publication date: August 4, 2005Applicant: Renesas Technology Corp.Inventors: Yasuyoshi Itoh, Shuuichi Ueno, Haruo Furuta, Natsuo Ajika
-
Patent number: 6867455Abstract: A semiconductor device capable of holding multibit information in one memory cell, and a method of manufacturing the semiconductor device. A trench is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film of a gate insulating film which interpose the trench are caused to function as first and second electric charge holding portions capable of holding electric charges. In the case in which first electric charges are trapped on the drain side and second electric charges are trapped on the source side, a portion of a gate electrode in the trench functions as a shield. If a fixed potential is given to the gate electrode, the second electric charge holding portion is not influenced by an electric field induced by the first electric charges so that the trapping of the second electric charges is not inhibited.Type: GrantFiled: June 23, 2003Date of Patent: March 15, 2005Assignee: Renesas Technology Corp.Inventors: Yasuyoshi Itoh, Shuuichi Ueno, Haruo Furuta, Natsuo Ajika
-
Patent number: 6737336Abstract: A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilicon film.Type: GrantFiled: June 28, 2002Date of Patent: May 18, 2004Assignee: Renesas Technology Corp.Inventors: Shuuichi Ueno, Yasuo Inoue, Masayoshi Shirahata
-
Patent number: 6734523Abstract: A semiconductor device including a well divided into a plurality of parts by a trench, to effect a reduction in layout area, and a manufacturing method thereof. In the semiconductor device, an element isolation film is formed such as to have to a depth from the main surface of a semiconductor substrate, and the area from the main surface of the substrate to the depth is divided into a plurality of first regions. A first well is formed in each of the first regions. A second well is formed in a second region deeper than the first well in the substrate, and the second well is in contact with some of the first wells.Type: GrantFiled: September 14, 1999Date of Patent: May 11, 2004Assignee: Renesas Technology Corp.Inventors: Shuuichi Ueno, Tomohiro Yamashita, Hidekazu Oda
-
Publication number: 20040056315Abstract: A semiconductor device having a MOS transistor capable of effectively reducing leakage current and a method of manufacturing the same are provided. A silicon nitride film (11) is formed at the interface between a silicon substrate (1) and an oxide film (2) in the area except for the region for forming a polysilicon gate electrode (3) (i.e., an out-of-gate-electrode region). A silicon nitride film (13) is formed at the interface between the oxide film (2) and the side surface of the polysilicon gate electrode (3). Since the silicon nitride films (11, 13) can suppress the progress of oxidation, the oxidation of the silicon substrate (1) and the polysilicon gate electrode (3) can be suppressed effectively during a smile oxidation processing for obtaining the final shape of the oxide film (2).Type: ApplicationFiled: September 24, 2003Publication date: March 25, 2004Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shuuichi Ueno, Akinobu Teramoto
-
Publication number: 20040026745Abstract: It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TR1) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.Type: ApplicationFiled: June 23, 2003Publication date: February 12, 2004Applicant: RenesasTechnology Corp.Inventors: Yasuyoshi Itoh, Shuuichi Ueno, Haruo Furuta, Natsuo Ajika
-
Patent number: 6503799Abstract: There is provided a method of forming an element isolation structure that can maintain its element isolation capability even with the progress of miniaturization of semiconductor elements. Through thermal processing in a nitrogen atmosphere at 900° C., a non single-crystal silicon film (80) is crystallized into single-crystal form by epitaxial growth on the main surface of a substrate, thereby to form an epitaxial silicon film (85). The epitaxial silicon film (85) is then planarized by CMP to expose the upper surface of an element isolation insulating film (50). This completes the element isolation insulating film (50) having a two-level protruding shape.Type: GrantFiled: November 26, 2001Date of Patent: January 7, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuyuki Horita, Takashi Kuroi, Shuuichi Ueno
-
Patent number: 6498077Abstract: Provided are a semiconductor device having a MOS transistor of a structure capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and leak current reduction, as well as a method of manufacturing the same. That is, in addition to the usual MOS transistor structure, a channel dope region (1) is disposed at a predetermined depth so as to extend substantially the entire surface of a flat surface in a P well region (22) including a channel region. In the channel dope region (1), it is set so that the maximum value of the P type impurity concentration (MAX of P) ranges from 1×1018 to 1×1019, and the maximum value of the N type impurity concentration (MAX of N) of a source/drain region (31 (32)) is not less than 10% and not more than 100%. Note that the surface proximate region of the P well region (22) is to be beyond the object.Type: GrantFiled: March 26, 2001Date of Patent: December 24, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shuuichi Ueno, Katsuyuki Horita, Takashi Kuroi
-
Publication number: 20020167066Abstract: A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilicon film.Type: ApplicationFiled: June 28, 2002Publication date: November 14, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shuuichi Ueno, Yasuo Inoue, Masayoshi Shirahata
-
Publication number: 20020149080Abstract: Provided are a semiconductor device in which a well is divided into a plurality of parts by a trench, to effect a reduction in layout area, and a manufacturing method thereof. In the semiconductor device, an element isolation film (T) is formed such as to have to a depth (L1) from the main surface of a semiconductor substrate (100), and the area from the main surface of the substrate (100) to the depth (L1) is divided into a plurality of first regions (R1). A first well (W1) is formed in each of the first regions (R1). A second well (W2) is formed in a second region (R2) deeper than the first well (W1) in the substrate (100), and the second well (W2) is in contact with some of the first wells (W1).Type: ApplicationFiled: September 14, 1999Publication date: October 17, 2002Inventors: SHUUICHI UENO, TOMOHIRO YAMASHITA, HIDEKAZU ODA
-
Publication number: 20020130373Abstract: A semiconductor device having a MOS transistor capable of effectively reducing leakage current and a method of manufacturing the same are provided. A silicon nitride film (11) is formed at the interface between a silicon substrate (1) and an oxide film (2) in the area except for the region for forming a polysilicon gate electrode (3) (i.e., an out-of-gate-electrode region). A silicon nitride film (13) is formed at the interface between the oxide film (2) and the side surface of the polysilicon gate electrode (3). Since the silicon nitride films (11, 13) can suppress the progress of oxidation, the oxidation of the silicon substrate (1) and the polysilicon gate electrode (3) can be suppressed effectively during a smile oxidation processing for obtaining the final shape of the oxide film (2).Type: ApplicationFiled: August 14, 2001Publication date: September 19, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shuuichi Ueno, Akinobu Teramoto
-
Patent number: 6417555Abstract: A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilcon film.Type: GrantFiled: January 6, 1999Date of Patent: July 9, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shuuichi Ueno, Yasuo Inoue, Masayoshi Shirahata
-
Publication number: 20020028568Abstract: Provided are a semiconductor device having a MOS transistor of a structure capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and leak current reduction, as well as a method of manufacturing the same. That is, in addition to the usual MOS transistor structure, a channel dope region (1) is disposed at a predetermined depth so as to extend substantially the entire surface of a flat surface in a P well region (22) including a channel region. In the channel dope region (1), it is set so that the maximum value of the P type impurity concentration (MAX of P) ranges from 1×1018 to 1×1019, and the maximum value of the N type impurity concentration (MAX of N) of a source/drain region (31 (32)) is not less than 10% and not more than 100%. Note that the surface proximate region of the P well region (22) is to be beyond the object.Type: ApplicationFiled: March 26, 2001Publication date: March 7, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shuuichi Ueno, Katsuyuki Horita, Takashi Kuroi