Abstract: A laterally diffused metal oxide semiconductor device and a preparation method thereof are disclosed. The semiconductor device includes: a substrate; a body region having a first conductivity type and formed in the substrate; a drift region, having a second conductivity type, formed in the substrate and adjacent to the body region; a field plate structure, formed on the drift region, a lower surface of an end of the field plate structure close to the body region being flush with the upper surface of the substrate, and the end of the field plate structure close to the body region also having an upwardly extending inclined surface; and a drain region, having a second conductivity type, formed in an upper layer of the drift region, and in contact with the end of the field plate structure away from the body region.

Abstract: A battery module and an electric vehicle are provided by the present application. The battery module includes a case body and at least one tray; at least one exhaust port is defined in the case body, at least one tray mounting cavity is defined in the case body, and the case body includes a first mounting surface surrounding a periphery of the tray; the tray is disposed in the tray mounting cavity to divide the tray mounting cavity into a cell accommodating cavity located above the tray and a pressure relief cavity located below the tray, the tray is provided with through holes facing battery cells, the pressure relief cavity is communicated with the through holes and the exhaust port, respectively, and the cell accommodating cavity is configured to accommodate the battery cells; the tray includes a second mounting surface, and the second mounting surface abuts against the first mounting surface.

Abstract: The present disclosure provides a universal preparation method for in-situ growth of a layered double hydroxide (LDH) layer on a substrate surface, and belongs to the technical field of material synthesis. In the present disclosure, an LDH protective layer is grown in situ on a surface of a substrate by means of electrodeposition combined with hydrothermal treatment. Specifically, a seed crystal layer of the LDH is formed on the substrate surface by the electrodeposition, and then obtained LDH seed crystals are crystallized and grown by Ostwald ripening through the hydrothermal treatment. In this way, the LDH protective layer is formed in which an interlayer anion is a nitrate. The protective layer protects the substrate against corrosion. Moreover, since the interlayer anion is the nitrate, the protective layer can be exchanged with other corrosion-inhibiting anions, and is modifiable.

Abstract: A memory circuit includes first and second inverters that are cross coupled. The first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit. The first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.

Abstract: Provided are a tumor immune enhancer, a pharmaceutical composition thereof, and a preparation method therefor. The enhancer comprises one or more polypeptides using sequences shown in SEQ ID NOs.: 1-9 as core structures, and can be used for preparing tumor vaccines.

Abstract: A method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a semiconductor substrate of a first conductivity type, forming a deep well of a second conductivity type in the semiconductor substrate, forming a channel region of the first conductivity type, a first well region of the first conductivity type, and a drift region of the second conductivity type in the deep well, the first well region and the channel region being spaced by a portion of the deep well, the drift region being located between the channel region and the first well region, forming an ion implantation region of the first conductivity type in the deep well, the ion implantation region being located under the drift region, and forming a source region of the second conductivity type and a drain region of the second conductivity type in the deep well.

Abstract: A system for high-value utilization of organic solid waste includes an anaerobic digestion unit, a biogas measurement and collection unit and a methane purification and liquefaction unit. The anaerobic digestion unit includes an organic solid waste pretreatment system and an anaerobic digestion device. The biogas measurement and collection unit includes a gas flow meter and a high-pressure biogas collection device. The methane purification and liquefaction unit includes a high-pressure separation tank, a liquefaction pretreatment system, a heavy hydrocarbon and benzene removal device, a two-stage rectification system, a low-temperature pressure liquid storage tank device and a buffer storage tank. The organic solid waste undergoes an anaerobic digestion treatment to produce methane followed by collection, purification and liquefaction.

Abstract: Provided is a method for evaluating a pretreatment effect for organic solid waste based on fractal dimension, relating to biological conversion of organic solid waste. Samples of the organic solid waste are collected, and dried and broken up to obtain dried samples. The mixtures obtained are analyzed using a laser particle size analyzer, so as to measure a wave vector Q and a scattering intensity I of each of the mixtures. According to a fractal theory, the wave vector Q and the scattering intensity I obtained are analyzed using a data processing software to obtain a two-dimensional fractal dimension Df of each of the samples. Based on data from documents and experiments, a total organic carbon or an apparent activated energy is evaluated, so as to evaluate the pretreatment effects of samples of the organic solid waste.

Abstract: A system for high-value utilization of organic solid waste includes an anaerobic digestion unit, a biogas measurement and collection unit and a methane purification and liquefaction unit. The anaerobic digestion unit includes an organic solid waste pretreatment system and an anaerobic digestion device. The biogas measurement and collection unit includes a gas flow meter and a high-pressure biogas collection device. The methane purification and liquefaction unit includes a high-pressure separation tank, a liquefaction pretreatment system, a heavy hydrocarbon and benzene removal device, a two-stage rectification system, a low-temperature pressure liquid storage tank device and a buffer storage tank. The organic solid waste undergoes an anaerobic digestion treatment to produce methane followed by collection, purification and liquefaction.

Abstract: Provided is a method for evaluating a pretreatment effect for organic solid waste based on fractal dimension, relating to biological conversion of organic solid waste. Samples of the organic solid waste are collected, and dried and broken up to obtain dried samples. The mixtures obtained are analyzed using a laser particle size analyzer, so as to measure a wave vector Q and a scattering intensity I of each of the mixtures. According to a fractal theory, the wave vector Q and the scattering intensity I obtained are analyzed using a data processing software to obtain a two-dimensional fractal dimension Df of each of the samples. Based on data from documents and experiments, a total organic carbon or an apparent activated energy is evaluated, so as to evaluate the pretreatment effects of samples of the organic solid waste.

Abstract: In one embodiment, a capacitor structure includes a substrate, a dielectric stack, a first conductor segment, a second conductor segment and a shielding conductor segment. The dielectric stack is formed on the substrate. A first layer of the dielectric stack includes a plurality of conductor segments routed only in a first direction. A first conductor segment among the multiple conductor segments may be biased to a first voltage. The second conductor segment among the multiple conductor segments may be biased to a second voltage. The shielding conductor segment may be biased to the second voltage and is formed at an end of the first conductor segment. In addition to that, the capacitances for the capacitor structure may be adjusted while the footprint of the capacitor structure is fixed.

Abstract: In one embodiment, a capacitor structure includes a substrate, a dielectric stack, a first conductor segment, a second conductor segment and a shielding conductor segment. The dielectric stack is formed on the substrate. A first layer of the dielectric stack includes a plurality of conductor segments routed only in a first direction. A first conductor segment among the multiple conductor segments may be biased to a first voltage. The second conductor segment among the multiple conductor segments may be biased to a second voltage. The shielding conductor segment may be biased to the second voltage and is formed at an end of the first conductor segment. In addition to that, the capacitances for the capacitor structure may be adjusted while the footprint of the capacitor structure is fixed.

Abstract: An integrated circuit includes a buffer circuit, a receiving circuit, and a programmable repeater circuit. The programmable repeater circuit includes a routing input and an enable input. The programmable repeater circuit buffers an input signal received at the routing input from the buffer circuit through a first conductor to generate an output signal that is provided to an input of the receiving circuit through a second conductor only in response to an enable signal at the enable input enabling the programmable repeater circuit.

Abstract: An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit block in the integrated circuit with a selected power supply signal.

Abstract: Apparatus for integrated capacitors and associated methods are disclosed. In one embodiment, an integrated capacitor includes a first plurality of metal members that are fabricated using a first plurality of metal layers, and are oriented in a first orientation. The integrated capacitor also includes a second plurality of metal members that are fabricated using a second plurality of metal layers. The second plurality of metal members are oriented transverse to the first orientation. The integrated capacitor further includes a third plurality of metal members, which are fabricated using a third plurality of metal layers, and are oriented in the first orientation.

Abstract: In one embodiment, an integrated circuit is described. The integrated circuit includes a substrate, a dielectric stack, a first inductor and a second inductor. The dielectric stack may be formed above the substrate and includes first and second layers. The first inductor may be formed in both the first and second layers. The second inductor may also be formed in the first and second layers with a substantial portion of the first inductor structure overlaps with the second inductor structure.

Abstract: An integrated circuit system, and a method of manufacture thereof, includes: an integrated circuit substrate; and a discretized tunable precision resistor having a total resistance including: a resistor body over the integrated circuit substrate, interconnects directly on the resistor body, metal taps directly on the interconnects and at opposing sides of the resistor body, and conductive metal strips over the interconnects, wherein the total resistance is a function of an active resistor length of the resistor body between a pair of the metal taps in contact with two of the conductive metal strips.

Abstract: An integrated circuit may include interconnects formed from alternating metal interconnect layers and inter-metal dielectric layers. A metal-insulator-metal capacitor may be formed within a selected inter-metal dielectric layer. The metal-insulator-metal capacitor may include first and second capacitor electrodes. The first capacitor electrode may contact a first conductive interconnect line in an underlying metal interconnect layer. The second capacitor electrode may overlap the first capacitor electrode and a portion of a second conductive interconnect line in the underlying metal layer. A via may be formed between the underlying metal interconnect layer and an additional metal interconnect layer. The via may simultaneously contact the second capacitor electrode and the second conductive interconnect line.

Abstract: A capacitor structure having a complete terminal shield is provided. The capacitor structure may include a first conductive segment with a first set of conductive fingers and a second segment structure with a second set of conductive fingers. The second set of conductive fingers may be spatially interleaved with the first set of conductive fingers in the first conductive structure. The first conductive segment may receive a first voltage, whereas the second conductive segment may receive a second voltage that is different than the first voltage. The capacitor structure further includes a conductive shielding structure that is connected to the first conductive segment. The conductive shielding structure may laterally surround the second conductive segment from at least three sides. An additional conductive shielding structure that connects to the first and second conductive segments is formed directly above the first and second conductive segments.

Abstract: An inductor may be formed from a conductive path that includes intertwined conductive lines. There may be two, three, or more than three intertwined conductive lines in the conductive path. The conductive lines may be formed from conductive structures in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers that include conductive traces and may include via layers that include vias for interconnecting the traces. The intertwined conductive lines may be formed from the conductive structures in the metal and via layers. In crossover regions, the conductive lines may cross each other without electrically connecting to each other. Vias may be used to couple multiple layers of traces together to reduce line resistance.