Abstract: Methods and systems for detection of an endpoint of a substrate process are provided. A set of machine learning models are trained to provide a metrology measurement value associated with a particular type of metrology measurement for a substrate based on spectral data collected for the substrate. A respective machine learning model is selected to be applied to future spectral data collected during a future substrate process for a future substrate in view of a performance rating associated with the particular type of metrology measurement. Current spectral data is collected during a current process for a current substrate and provided as input to the respective machine learning model. An indication of a respective metrology measurement value corresponding to the current substrate is extracted from one or more outputs of the trained machine learning model.

Abstract: A method includes determining that conditions of a processing chamber have changed since a trained machine learning model associated with the processing chamber was trained. The method further includes determining whether a change in the conditions of the processing chamber is a gradual change or a sudden change. Responsive to determining that the change in the conditions of the processing chamber is a gradual change, the method further includes performing a first training process to generate a new machine learning model. Responsive to determining that the change in the conditions of the processing chamber is a sudden change, the method further includes performing a second training process to generate the new machine learning model. The first training process is different from the second training process.

Abstract: Methods and systems for detection of an endpoint of a substrate process are provided. A set of machine learning models are trained to provide a metrology measurement value associated with a particular type of metrology measurement for a substrate based on spectral data collected for the substrate. A respective machine learning model is selected to be applied to future spectral data collected during a future substrate process for a future substrate in view of a performance rating associated with the particular type of metrology measurement. Current spectral data is collected during a current process for a current substrate and provided as input to the respective machine learning model. An indication of a respective metrology measurement value corresponding to the current substrate is extracted from one or more outputs of the trained machine learning model.

Abstract: A machine learning model trained to provide metrology measurements for a substrate is provided. Training data generated for a prior substrate processed according to a prior process is provided to train the model. The training data includes a training input including a subset of historical spectral data extracted from a normalized set of historical spectral data collected for the prior substrate during the prior process. The subset of historical spectral data includes an indication of historical spectral features associated with a particular type of metrology measurement. The training data also includes a training output including a historical metrology measurement obtained for the prior substrate, the historical metrology measurement associated with the particular type of metrology measurement. Spectral data is collected for a current substrate processed according to a current process.

Abstract: The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.

Abstract: The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.

Abstract: A method of designing an integrated circuit, that includes receiving a first list corresponding to at least one circuit component in a layout, generating a condensed layout from the layout and performing an electrostatic discharge (ESD) check of the condensed layout. The condensed layout is generated by a processor. The ESD check is configured to verify compliance with one or more ESD design rules. The condensed layout includes at least one circuit component. The at least one circuit component includes an ESD circuit and an associated ESD current path.

Abstract: A method of designing an integrated circuit, that includes receiving a first list corresponding to at least one circuit component in a layout, generating a condensed layout from the layout and performing an electrostatic discharge (ESD) check of the condensed layout. The condensed layout is generated by a processor. The ESD check is configured to verify compliance with one or more ESD design rules. The condensed layout includes at least one circuit component. The at least one circuit component includes an ESD circuit and an associated ESD current path.

Abstract: A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.

Abstract: A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.

Abstract: System and method for hierarchy reconstruction from a flattened layout are described. In one embodiment, a method for producing a reconstructed layout for an integrated circuit design from an original layout and a revised layout includes, for each pattern of the original layout, determining a pattern of the revised layout that corresponds to the pattern of the original layout; and assigning the corresponding pattern of the revised layout to a temporary instance, the temporary instance corresponding to an instance of the pattern of the original layout and citing to a temporary cell. The method further includes creating a temporary reconstructed layout from the temporary instances; and producing the reconstructed layout from the temporary reconstructed layout, wherein a hierarchy of the reconstructed layout is similar to a hierarchy of the original layout.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.