Abstract: Methods and circuits are provided for controlling a signal applied to a control terminal of a variable voltage attenuator. In one embodiment, a method comprises detecting an output signal of the variable voltage attenuator, generating a logarithm of the detected output signal of the variable voltage attenuator, and generating the signal applied to the control terminal of the variable voltage attenuator at least partially based on the logarithm of the detected output signal of the variable voltage attenuator.

Abstract: A transistor cell includes a first stage comprising a first transistor that is coupled to a RC filter arrangement. A second stage has a second transistor that is coupled to the first stage. The linearity of the transistor cell is improved by shifting the DC bias point so that the first stage is biased at a high quiescent current while the second stage is biased at a low quiescent current.

Abstract: A high performance single-pole-double-throw (SPDT) Transmitter/Receiver (T/R) FET switch utilizes a plurality of multi-gate FETs in series to realize low insertion loss, low harmonic distortion and high power handling capabilities. The SPDT switch consists of an antenna port, a transmitter branch coupled to a transmitter port through a plurality of multi-gate FETs in series and a receiver branch coupled to a receiver port through a plurality of multi-gate FETs in series. When a high power signal passes from the transmitter port to the antenna port through the transmitter branch, the receiver branch is required to be shut off electrically to prevent the high power signal from leaking to receiver port. This leakage can degrade the isolation of the switch and cause harmonic distortion. Furthermore, the transmitter branch is required to provide a resistance as small as possible to reduce the power loss when it passes through the transmitter branch to the antenna port.

Abstract: A SPDT switch includes an antenna port. A transmitter section is coupled to a transmitter port. The transmitter section includes a plurality of transistors that are coupled in series relative to each other. A receiver section is coupled to a receiver port. The receiver section includes a plurality of transistors that are coupled in series relative to each other, so that when the transmitter section transmits high power to the antenna port, the receive section is effectively off to provide isolation to the receive port. The receiver port is coupled to the receiver section using at least one external capacitor. The at least one external capacitor is used to improve the power handling capability and harmonic performance of the switch.

Abstract: A high performance single-pole-double-throw (SPDT) Transmitter/Receiver (T/R) FET switch utilizes a plurality of multi-gate FETs in series to realize low insertion loss, low harmonic distortion and high power handling capabilities. The SPDT switch consists of an antenna port, a transmitter branch coupled to a transmitter port through a plurality of multi-gate FETs in series and a receiver branch coupled to a receiver port through a plurality of multi-gate FETs in series. When a high power signal passes from the transmitter port to the antenna port through the transmitter branch, the receiver branch is required to be shut off electrically to prevent the high power signal from leaking to receiver port. This leakage can degrade the isolation of the switch and cause harmonic distortion. Furthermore, the transmitter branch is required to provide a resistance as small as possible to reduce the power loss when it passes through the transmitter branch to the antenna port.

Abstract: An improved bipolar transistor power amplifier circuit including a bias input node, an RF input node, an RF output node, and a plurality of HBTs. Each HBT includes a base, an emitter, a collector, a base resistor connected to the base and selected to offset a portion of the voltage drop across the base and emitter of each transistor, an emitter resistor connected to the emitter, and a base capacitor having two electrodes one of which is coupled to the base. The HBTs are grouped together in two or more groups and each group includes a base resistor selected to offset another portion of the voltage drop across the base and emitter of the transistors.

Abstract: An improved bipolar transistor power amplifier circuit including a bias input node, an RF input node, an RF output node, and a plurality of HBTs. Each HBT includes a base, an emitter, a collector, a base resistor connected to the base and selected to offset a portion of the voltage drop across the base and emitter of each transistor, an emitter resistor connected to the emitter, and a base capacitor having two electrodes one of which is coupled to the base. The HBTs are grouped together in two or more groups and each group includes a base resistor selected to offset another portion of the voltage drop across the base and emitter of the transistors.

Abstract: An amplifier circuit and fabrication method including a bias input node, an RF input node, an RF output node, and a plurality of amplifier cells. Each cell has a plurality of discrete emitter contacts of a first conductivity type, a plurality of discrete base contacts of a second conductivity type and grouped in two or more groups, at least one collector contact of the first conductivity type connected to the RF output node, and a base capacitor for each group having two electrodes: an input electrode coupled to the RF input node and an output electrode coupled to a group of discrete base contacts. There is also a base resistor for each group having an input coupled to the bias input node and an output coupled to a group of discrete base contacts. An emitter resistor is coupled to each discrete emitter contact to provide more effective base ballasting and thermal stability than with a cascode arrangement of HBT transistors.

Abstract: A power controller circuit for a power amplifier stage includes an exponential power control circuit responsive to a power control signal for providing an exponential control current to control power amplifier stage and linear power control circuit responsive to the power control signal for supplementing the exponential control current to the power amplifier stage with a linear control current to produce a composite control current with a reduced and extended slope.

Abstract: A power controller circuit for a power amplifier stage includes an exponential power control circuit responsive to a power control signal for providing an exponential control current to control power amplifier stage and linear power control circuit responsive to the power control signal for supplementing the exponential control current to the power amplifier stage with a linear control current to produce a composite control current with a reduced and extended slope.

Abstract: An electronic switch structure is disclosed. Capacitors are employed to bias gate-source and gate-drain connections in multi-gate or multi-FET structures achieving linear switch operation over a wide range of signal input power values.