Abstract: The disclosure relates to a method of fabricating an enhancement mode Group III-nitride HEMT device and a Group III-nitride structure fabricated therefrom. One example embodiment is a method for fabricating an enhancement mode Group III-nitride HEMT device. The method includes providing a structure. The structure includes a substrate having a main surface. The structure also includes a layer stack overlying the main surface. Each layer of the layer stack includes a Group III-nitride material. The structure further includes a capping layer on the layer stack. The method also includes forming a recessed gate region by removing, in a gate region, at least the capping layer by performing an etch process, thereby exposing a top surface of an upper layer of the layer stack. The method further includes forming a p-type doped GaN layer in the recessed gate region and on the capping layer by performing a non-selective deposition process.

Abstract: The disclosure relates to a method of fabricating an enhancement mode Group III-nitride HEMT device and a Group III-nitride structure fabricated therefrom. One example embodiment is a method for fabricating an enhancement mode Group III-nitride HEMT device. The method includes providing a structure. The structure includes a substrate having a main surface. The structure also includes a layer stack overlying the main surface. Each layer of the layer stack includes a Group III-nitride material. The structure further includes a capping layer on the layer stack. The method also includes forming a recessed gate region by removing, in a gate region, at least the capping layer by performing an etch process, thereby exposing a top surface of an upper layer of the layer stack. The method further includes forming a p-type doped GaN layer in the recessed gate region and on the capping layer by performing a non-selective deposition process.

Abstract: An integrated circuit comprising a first III-N transistor having a source region and a second III-N transistor having a source region, both transistors being monolithically integrated on a common silicon substrate of a first doping type and separated from each-other by an isolation region, the substrate comprising underneath the first transistor a well of a first doping type electrically connected to the source region of the first transistor and comprising underneath the second transistor a well of a second doping type electrically connected to the source region of the second transistor, thereby forming a junction diode in the substrate between the sources of the first and the second transistor.