Patents by Inventor Shuzo Akejima

Shuzo Akejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12074130
    Abstract: An electronic circuit device includes a plane-shaped shield member having conductivity, at least one electronic circuit element having a first surface opposed to a second surface on which a connecting part is formed, the first surface arranged on the plane-shaped shield member, a rewiring layer comprises an insulating photosensitive resin layer enclosing the electronic circuit element on the plane-shaped shield member, a plurality of wiring photo vias having a plurality of first conductors electrically connected to a connecting part of the electronic element, a wiring having a second conductor electrically connected to each of the plurality of wiring photo vias on the same surface parallel to the plane-shaped shield member, and a wall-shaped shield groove having a third conductor for a sealing arranged to surround a thickness direction of the electronic circuit element.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: August 27, 2024
    Assignee: RISING TECHNOLOGIES CO., LTD.
    Inventor: Shuzo Akejima
  • Patent number: 12009282
    Abstract: A memory device includes: a wiring substrate including a multilevel wiring layer and first and second surfaces at opposite sides; a control element embedded in the wiring substrate and having first and second element surfaces at opposite sides, with multiple electrode pads connected to the multilevel wiring layer at the first element surface; a first heat dissipation member at a region of the first surface overlapping the control element; a heat dissipation structure facing the second element surface and exposed at the second surface; and at least one memory element connected with the multilevel wiring layer at a first surface region not overlapping the control element. The multilevel wiring layer includes a signal pattern electrically connecting the control element with the memory element or the external connection terminal, and a heat dissipation conductor pattern forming a heat dissipation path between the control element and the first heat dissipation member.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: June 11, 2024
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventor: Shuzo Akejima
  • Publication number: 20230411237
    Abstract: A memory device includes: a wiring substrate including a multilevel wiring layer and first and second surfaces at opposite sides; a control element embedded in the wiring substrate and having first and second element surfaces at opposite sides, with multiple electrode pads connected to the multilevel wiring layer at the first element surface; a first heat dissipation member at a region of the first surface overlapping the control element; a heat dissipation structure facing the second element surface and exposed at the second surface; and at least one memory element connected with the multilevel wiring layer at a first surface region not overlapping the control element. The multilevel wiring layer includes a signal pattern electrically connecting the control element with the memory element or the external connection terminal, and a heat dissipation conductor pattern forming a heat dissipation path between the control element and the first heat dissipation member.
    Type: Application
    Filed: March 11, 2021
    Publication date: December 21, 2023
    Inventor: Shuzo AKEJIMA
  • Patent number: 11696400
    Abstract: An embedded module according to the present invention includes a base substrate having a multi-layer wiring, at least two semiconductor chip elements having different element thicknesses, each of the semiconductor chip element having a first surface fixed to the base substrate and having a connection part on a second surface, an insulating photosensitive resin layer enclosing the semiconductor chip elements on the base substrate and being formed by a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the semiconductor chip elements, the second wiring photo via arranged at the outer periphery of each of the semiconductor chip elements and electrically connected to a connection part of the base substrate, the wiring arranged so as to be orthogonal to and electrically connected to the first wiring photo via and the second wiring photo via.
    Type: Grant
    Filed: February 6, 2022
    Date of Patent: July 4, 2023
    Assignee: RISING TECHNOLOGIES CO., LTD.
    Inventor: Shuzo Akejima
  • Patent number: 11557542
    Abstract: An electronic circuit device according to the present invention includes a base substrate including a wiring layer having a connection part, at least one electronic circuit element, and a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing a surface on which a connection part of the electronic circuit element is formed and a side surface of the electronic circuit element and embedding a first wiring photo via, a second wiring photo via and a wiring, the first wiring photo via directly connected to the connection part of the electronic circuit element, the second wiring photo via arranged at the outer periphery of the electronic circuit element and directly connected to a connection part of the wiring layer, the wiring electrically connected to the first wiring photo via and the second wiring photo via on a same surface.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 17, 2023
    Assignee: RISING TECHNOLOGIES CO., LTD.
    Inventor: Shuzo Akejima
  • Publication number: 20220167503
    Abstract: An embedded module according to the present invention includes a base substrate having a multi-layer wiring, at least two semiconductor chip elements having different element thicknesses, each of the semiconductor chip element having a first surface fixed to the base substrate and having a connection part on a second surface, an insulating photosensitive resin layer enclosing the semiconductor chip elements on the base substrate and being formed by a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the semiconductor chip elements, the second wiring photo via arranged at the outer periphery of each of the semiconductor chip elements and electrically connected to a connection part of the base substrate, the wiring arranged so as to be orthogonal to and electrically connected to the first wiring photo via and the second wiring photo via.
    Type: Application
    Filed: February 6, 2022
    Publication date: May 26, 2022
    Applicant: RISING TECHNOLOGIES CO., LTD.
    Inventor: Shuzo AKEJIMA
  • Patent number: 11330712
    Abstract: An electronic circuit device according to the present invention includes a base substrate having a wiring layer, at least one first electronic circuit element having a first surface fixed to the base substrate and having a connection part on a second surface opposed to the first surface, a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing the first electronic circuit element on the base substrate and embedding a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the first electronic circuit element, the second wiring photo via arranged at the outer periphery of the first electronic circuit element and electrically connected to a connection part of the wiring layer, the wiring arranged on the second surface and electrically connected to the first wiring photo via and the second wiring photo via.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 10, 2022
    Assignee: RISING TECHNOLOGIES CO., LTD.
    Inventor: Shuzo Akejima
  • Publication number: 20220084974
    Abstract: An electronic circuit device according to the present invention includes a plane-shaped shield member having conductivity, at least one electronic circuit element having a first surface opposed to a second surface on which a connecting part is formed, the first surface arranged on the plane-shaped shield member, a rewiring layer comprises an insulating photosensitive resin layer enclosing the electronic circuit element on the plane-shaped shield member, a plurality of wiring photo vias having a plurality of first conductors electrically connected to a connecting part of the electronic element, a wiring having a second conductor electrically connected to each of the plurality of wiring photo vias on the same surface parallel to the plane-shaped shield member, and a wall-shaped shield groove having a third conductor for a sealing arranged to surround a thickness direction of the electronic circuit element.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 17, 2022
    Applicant: RISING TECHNOLOGIES CO., LTD.
    Inventor: Shuzo AKEJIMA
  • Patent number: 11189571
    Abstract: The electronic circuit device according to the present invention including the wiring layer 13 including a plurality of the metal wirings, the photosensitive resin layer 21 made of the photosensitive resin arranged on the wiring layer 13, and the first electronic circuit element 33 arranged in the photosensitive resin layer 21. In this electronic circuit device, a plurality of opening 41 for exposing a part of the wiring layer 13 is formed on the photosensitive resin layer 21, and further, together with three-dimensionally connected to the first electronic circuit element 33, the re-distribution layer 42 on the first electronic circuit element including a plurality of the metal wirings which is three-dimensionally connected via a plurality of openings to a part of the wiring layer 13, and the first external connection terminal 51 connected to the re-distribution layer 42 are formed.
    Type: Grant
    Filed: March 7, 2020
    Date of Patent: November 30, 2021
    Assignee: RISING TECHNOLOGIES CO., LTD.
    Inventor: Shuzo Akejima
  • Publication number: 20210084762
    Abstract: An electronic circuit device according to the present invention includes a base substrate having a wiring layer, at least one first electronic circuit element having a first surface fixed to the base substrate and having a connection part on a second surface opposed to the first surface, a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing the first electronic circuit element on the base substrate and embedding a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the first electronic circuit element, the second wiring photo via arranged at the outer periphery of the first electronic circuit element and electrically connected to a connection part of the wiring layer, the wiring arranged on the second surface and electrically connected to the first wiring photo via and the second wiring photo via.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Applicant: RISING TECHNOLOGIES CO., LTD.
    Inventor: Shuzo AKEJIMA
  • Publication number: 20210082828
    Abstract: An electronic circuit device according to the present invention includes a base substrate including a wiring layer having a connection part, at least one electronic circuit element, and a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing a surface on which a connection part of the electronic circuit element is formed and a side surface of the electronic circuit element and embedding a first wiring photo via, a second wiring photo via and a wiring, the first wiring photo via directly connected to the connection part of the electronic circuit element, the second wiring photo via arranged at the outer periphery of the electronic circuit element and directly connected to a connection part of the wiring layer, the wiring electrically connected to the first wiring photo via and the second wiring photo via on a same surface.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Applicant: RISING TECHNOLOGIES CO., LTD.
    Inventor: Shuzo AKEJIMA
  • Publication number: 20210005555
    Abstract: The electronic circuit device according to the present invention including the wiring layer 13 including a plurality of the metal wirings, the photosensitive resin layer 21 made of the photosensitive resin arranged on the wiring layer 13, and the first electronic circuit element 33 arranged in the photosensitive resin layer 21. In this electronic circuit device, a plurality of opening 41 for exposing a part of the wiring layer 13 is formed on the photosensitive resin layer 21, and further, together with three-dimensionally connected to the first electronic circuit element 33, the re-distribution layer 42 on the first electronic circuit element including a plurality of the metal wirings which is three-dimensionally connected via a plurality of openings to a part of the wiring layer 13, and the first external connection terminal 51 connected to the re-distribution layer 42 are formed.
    Type: Application
    Filed: March 7, 2020
    Publication date: January 7, 2021
    Applicant: RISING TECHNOLOGIES CO., LTD.
    Inventor: Shuzo AKEJIMA
  • Publication number: 20120080801
    Abstract: A semiconductor device includes a circuit board having an element mounting area, connecting pads positioned in the same surface side as the element mounting area and external connectors to be connected with the connecting pads, respectively; and a semiconductor element mounted on the element mounting area of the circuit board and having electrode pads to be electrically connected with the connecting pads, respectively. The external connectors are detachably configured through a combination of convex portions and concave portions which are mechanically and electrically connected with one another.
    Type: Application
    Filed: December 9, 2011
    Publication date: April 5, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoru HARA, Shuzo AKEJIMA
  • Patent number: 8097950
    Abstract: A semiconductor device includes a circuit board having an element mounting area, connecting pads positioned in the same surface side as the element mounting area and external connectors to be connected with the connecting pads, respectively; and a semiconductor element mounted on the element mounting area of the circuit board and having electrode pads to be electrically connected with the connecting pads, respectively. The external connectors are detachably configured through a combination of convex portions and concave portions which are mechanically and electrically connected with one another.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: January 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoru Hara, Shuzo Akejima
  • Publication number: 20070159204
    Abstract: A semiconductor device includes a circuit board having an element mounting area, connecting pads positioned in the same surface side as the element mounting area and external connectors to be connected with the connecting pads, respectively; and a semiconductor element mounted on the element mounting area of the circuit board and having electrode pads to be electrically connected with the connecting pads, respectively. The external connectors are detachably configured through a combination of convex portions and concave portions which are mechanically and electrically connected with one another.
    Type: Application
    Filed: January 8, 2007
    Publication date: July 12, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoru Hara, Shuzo Akejima
  • Publication number: 20060055018
    Abstract: A plurality of signal processing semiconductor elements are stacked on or above a circuit board. A rewiring silicon chip is mounted on or above the circuit board. The rewiring silicon chip has an inner conductor layer for connection between the plural signal processing semiconductor elements and between the circuit board and the signal processing semiconductor elements. The circuit board and the plural signal processing semiconductor elements are electrically connected, and the plural signal processing semiconductor elements are electrically connected to each other. The interconnection of the plural signal processing semiconductor elements and the rearrangement of electrode pads of the signal processing semiconductor elements are realized by the rewiring silicon chip.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 16, 2006
    Inventors: Masahiro Sekiguchi, Chiaki Takubo, Shuzo Akejima