Patents by Inventor Shuzo Fujioka
Shuzo Fujioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120221863Abstract: The present invention aims to provide an authentication system that can accurately identify a genuine product. In an authentication system, a host instructs an authentication chip master to start authentication. In conjunction with the authentication start execution instruction, the host instructs a timer counter to start timer counting. In response to the authentication start execution instruction from the host, the authentication chip master outputs a challenge code to an authentication chip slave. The authentication chip slave performs an encryption process with respect to the challenge code. Then, the authentication chip slave outputs a response code obtained as the result of the encryption process, to the authentication chip master. Then, the authentication chip master performs a response code matching process, and outputs the authentication result to the host.Type: ApplicationFiled: February 8, 2012Publication date: August 30, 2012Inventors: Koji OSAKA, Shuzo Fujioka
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Patent number: 6813191Abstract: A microcomputer includes a nonvolatile memory for storing contents that can be erased from and written to the nonvolatile memory electrically when an erasing/writing voltage is supplied to the nonvolatile memory, and a processor for executing a program stored in the nonvolatile memory. The microcomputer also includes a setting element for setting a plurality of conditions for erasing contents from or writing contents into the nonvolatile memory, and an erasing/writing voltage supply enabler for enabling the erasing/writing voltage to be supplied to the nonvolatile memory when all of the plurality of conditions are satisfied.Type: GrantFiled: September 5, 2002Date of Patent: November 2, 2004Assignees: Renesas Technology Corp., Mitsubishi Electric System LSI Design CorporationInventor: Shuzo Fujioka
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Publication number: 20040128523Abstract: An information security microcomputer includes an encryption circuit encrypting and decrypting information, an authentication program authenticating an ICE main body, and a CPU performing entire control of the information security microcomputer. CPU stops at least a part of a function of the information security microcomputer when the ICE main body cannot be authenticated. Therefore, an unauthorized person cannot use the information security microcomputer as an ICE microcomputer so that security can be improved.Type: ApplicationFiled: July 10, 2003Publication date: July 1, 2004Applicants: RENESAS TECHNOLOGY CORP., RENESAS LSI DESIGN CORPORATIONInventor: Shuzo Fujioka
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Patent number: 6725375Abstract: There is provided a microcomputer including: an external apparatus discrimination means for discriminating that an external apparatus is connected to said microcomputer via an IC card interface section, based on a discrimination signal to be transmitted by said external apparatus, when the external apparatus is placed in a communicatable status which allows communication by feeding a power supply, a clock signal and initializing an operation; and memory contents change means for receiving data including a CPU program, from the external apparatus and executing changing of the contents of a memory, thereby allowing modification of a CPU program stored in the microcomputer during manufacture.Type: GrantFiled: December 6, 2000Date of Patent: April 20, 2004Assignees: Renesas Technology Corp., Mitsubishi Electric System LSI Design CorporationInventor: Shuzo Fujioka
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Patent number: 6658493Abstract: When reception data transmitted from a host computer is held in a transmission/reception buffer of a microcomputer, a reception flag is set to inhibit the holding of new data in the transmission/reception buffer. Also, when transmission data to be transmitted to the host computer is held in the transmission/reception buffer, a transmission flag is set to inhibit the holding of new data in the transmission/reception buffer. Though the reception flag is cleared in cases where the reception data is read out from the transmission/reception buffer to a central processing unit or the transmission flag is cleared in cases where the transmission data is read out from the transmission/reception buffer to the host computer, the central processing unit always clears the reception flag and the transmission flag before the central processing unit accesses to the transmission/reception buffer to read out the reception data or write next transmission data from/in the transmission/reception buffer.Type: GrantFiled: August 7, 2000Date of Patent: December 2, 2003Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design CorporationInventor: Shuzo Fujioka
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Publication number: 20030169624Abstract: A microcomputer includes a nonvolatile memory for storing contents that can be erased from and written to the nonvolatile memory electrically when an erasing/writing voltage is supplied to the nonvolatile memory, and a processor for executing a program stored in the nonvolatile memory. The microcomputer also includes a setting element for setting a plurality of conditions for erasing contents from or writing contents into the nonvolatile memory, and an erasing/writing voltage supply enabler for enabling the erasing/writing voltage to be supplied to the nonvolatile memory when all of the plurality of conditions are satisfied.Type: ApplicationFiled: September 5, 2002Publication date: September 11, 2003Inventor: Shuzo Fujioka
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Publication number: 20030005321Abstract: An information processing device is provided with a storage unit for storing key data used to perform encryption processing for data security as well as inversion of the key data, and an encryption processing unit for reading the key data together with the inversion of the key data from the storage unit, and for performing the encryption processing by using the key data read out of the storage unit.Type: ApplicationFiled: June 11, 2002Publication date: January 2, 2003Inventor: Shuzo Fujioka
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Patent number: 6480869Abstract: A random-number generating circuit comprising a plurality of shift registers synchronized with a clock and cascaded together, a circuit that obtains the sum of the outputs of more than one of the shift registers and inputs the obtained sum to the input terminal of the shift register on the first level, and a clock generating circuit that inputs a clock signal to each of the shift registers. One or more of the shift registers have external-signal input terminals and an addition circuit that adds bit data input through the external-signal input terminals to bit data of one or more of the bits stored within. The random-number generating circuit outputs as random-number data the bit data obtained from the addition by the addition circuit.Type: GrantFiled: July 30, 1999Date of Patent: November 12, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design CorporationInventor: Shuzo Fujioka
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Publication number: 20020013884Abstract: There is provided a microcomputer comprised of: an external apparatus discrimination means for discriminating an external apparatus connected via an IC card interface section, based on a discrimination signal to be transmitted, when a communicatable status is set by feeding a power supply and a clock signal and initializing an operation; and memory contents change means for receiving data from the external apparatus and executing contents change of a memory, thereby finding and modifying a failure of a CPU program.Type: ApplicationFiled: December 6, 2000Publication date: January 31, 2002Inventor: Shuzo Fujioka
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Patent number: 6198619Abstract: A capacitor network has an uncomplicated construction enabling the capacitance of the capacitor network to be easily increased or decreased. The capacitor network has a plurality of component capacitors formed from two metallic foil layers on opposite sides of a printed circuit board interconnected by lines disposed on both sides of said printed circuit board. The component capacitors of the capacitor network are arranged into at least one series circuit section and at least one parallel circuit section. The series circuit section includes two or more component capacitor, each including at least one component capacitor, connected in series. The parallel circuit section includes two or more parallel-connected component capacitor circuits, each including at least one component capacitor.Type: GrantFiled: November 2, 1998Date of Patent: March 6, 2001Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design CorporationInventor: Shuzo Fujioka
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Patent number: 6040786Abstract: A recognition system for non-contact IC cards that avoids the collision of response signals with a simple construction. A non-contact IC card in this system has a first transmitter that immediately transmits a response signal at a predetermined time slot for a first polling trial by the reader/writer and a second transmitter that transmits a response signal at a randomly time slot from a predetermined number of succeeding time slots, in response to a subsequent polling trial by the reader/writer. A reader/writer in this system has a polling unit that waits for the return of a response signal from a non-contact IC card at the predetermined time slot during the execution of a first polling trial and waits for the return of a response signal from a non-contact IC card at the randomly selected time slot during the execution of the subsequent polling trials.Type: GrantFiled: July 16, 1998Date of Patent: March 21, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Shuzo Fujioka
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Patent number: 5896325Abstract: An IC card having a memory for receiving data from and sending data to a data reader/writer includes a reading-completion detection circuit for detecting if each sense amplifier in the IC card has completed data reading from the memory and a control circuit which ignores a command sent from the data reader/writer when no reading completion detection signal is output from the data reading-completion detection circuit upon verifying a password sent from the data reader/writer.Type: GrantFiled: November 3, 1997Date of Patent: April 20, 1999Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Semiconductor Software Co., Ltd.Inventor: Shuzo Fujioka
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Patent number: 5837982Abstract: An antenna mechanism for a noncontacting IC card system for communication with a noncontacting IC card passing a gate, the antenna mechanism including an antenna; and a conductive shielding body located on an outer side of the gate to eliminate a communication area outside the gate by shielding electromagnetic waves from the antenna.Type: GrantFiled: April 21, 1997Date of Patent: November 17, 1998Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Semiconductor Software Co., Ltd.Inventor: Shuzo Fujioka
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Patent number: 5796943Abstract: A non-contact type IC card comprising a memory including a manufacturer code area and an error signal output circuit is disclosed. The error signal output circuit outputs an error signal such that an access from a read/write apparatus is allowed when a password coincidence is obtained when a predetermined code is stored in the manufacture code area. On the other hand, when the predetermined code is not stored in the manufacturer code area, the error signal output circuit outputs an error signal such that an access to all the memory area from the read/write apparatus is allowed regardless of a result of the password collation performed by the password collation circuit.Type: GrantFiled: May 31, 1996Date of Patent: August 18, 1998Assignees: Mitsubishi Electric Semiconductor Software Co., Ltd., Mitsubishi Denki Kabushiki KaishaInventor: Shuzo Fujioka
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Patent number: 5753902Abstract: A noncontact IC card, a card reader/writer, and a card system, for surely detecting a start flag, thereby reducing a communication error rate and achieving higher communication reliability. The noncontact IC card has a control unit, which includes a CPU, ROM, RAM, etc., and it further has a 1-bit flip-flop (F/F) connected between a receive circuit and the control unit. According to a program of the control unit, data are received one bit at a time, and a UART is set ready for receiving when a bit pattern of the start flag is detected. A card reader/writer is equipped with a control unit which includes a CPU, ROM, RAM, etc. The control unit inserts 1-byte dummy data "00.sub.H " between a trigger signal and the start flag at the time of transmission. A card system has a card reader/writer and a noncontact IC card.Type: GrantFiled: November 1, 1996Date of Patent: May 19, 1998Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Semiconductor Software Co., Ltd.Inventor: Shuzo Fujioka
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Patent number: 5727230Abstract: A reader/writer includes an input/output unit for inputting and outputting bidirectional signals from and to an external host computer, a transmitter/receiver for transmitting to and receiving from a noncontact IC card bidirectional electromagnetic-wave signals, the controller being electrically connected to the input/output unit and transmitter/receiver for transferring signals between them. The reader/writer thus assists in transferring signals between an external host computer and a noncontact IC card. The operation of the reader/writer is so simple that communication between a noncontact IC card and an external host computer can be achieved efficiently. The software implemented in the reader/writer need not be modified but can still cope with various application programs running in the noncontact IC card and external host computer.Type: GrantFiled: April 24, 1995Date of Patent: March 10, 1998Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Semiconductor Software Co., Ltd.Inventor: Shuzo Fujioka
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Patent number: 5719387Abstract: A non-contact type IC card includes a programmable memory divided into a user area for storing application data, and a system area for storing a system password and a system password effective code indicating requirement of collation of the system password. If the system area of the memory includes the system password effective code, access to the system area by an external apparatus is permitted only when passwords are identical as a result of password collation. If the system area does not include the system password effective code, the access by the external apparatus can be permitted without the password collation.Type: GrantFiled: July 14, 1995Date of Patent: February 17, 1998Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Semiconductor Software Co., Ltd.Inventor: Shuzo Fujioka
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Patent number: 5698836Abstract: In an IC card, a user area is set to have a first area in which a write password is made valid, and a second area in which a read password is made valid. When a write command for the first area is sent together with a password from a read/write apparatus, the password is collated with the write password. When a read command for the second area is sent together with a password, the password is collated with the read password. As a result of the collation, when the passwords are identical, the respective commands are executed.Type: GrantFiled: July 31, 1995Date of Patent: December 16, 1997Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Semiconductor Software Co., Ltd.Inventor: Shuzo Fujioka
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Patent number: 5661286Abstract: A noncontacting IC card system occupying a relatively small area without requiring a provision for a dead zone or unnecessary communication area outside a gate. A transmitting antenna 11 is provided between two contiguous gates i.e., on the inner sides of the gates, and receiving antennas are provided respectively toward the sides opposite to the transmitting antenna of the gates i.e., on the outer sides of the gates. It is thereby not necessary to provide a dead zone between the gates and an unnecessary communication area does not occur outside the gate.Type: GrantFiled: October 10, 1995Date of Patent: August 26, 1997Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Semiconductor Software Co., Ltd.Inventor: Shuzo Fujioka
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Patent number: 5619529Abstract: A non-contact IC card or a non-contact IC card reader/writer has an antenna for receiving a signal transmitted from the reader/writer or the IC card, a receiver circuit for demodulating the signal received by the receiving antenna and for converting the demodulated signal into a received data signal, a control circuit for data processing in response to the received data signal, a transmitter circuit for forming a transmission signal in response to a data signal supplied by the control circuit and for setting the transmission width of the transmission signal corresponding to one data bit to a value smaller than the signal width of one data bit, and a transmitting antenna for transmitting the transmission signal from the transmitter circuit to the reader/writer or the IC card.Type: GrantFiled: July 11, 1995Date of Patent: April 8, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Shuzo Fujioka