Patents by Inventor Shuzo Igarashi

Shuzo Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Characteristic amount calculating device for soldering inspection
    Patent number: 7308129
    Abstract: A characteristic amount calculating device for soldering inspection. The characteristic amount calculating device includes a design information inputting section for inputting design information of an inspection object, an inspection standard inputting section for inputting an inspection standard, a solder shape calculating section for calculating shape information of a solder fillet according to the design information, and an inspection image calculating section for calculating an inspection image according to the shape information.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: December 11, 2007
    Assignee: Fujitsu Limited
    Inventors: Masatomo Maida, Shuzo Igarashi
  • Characteristic amount calculating device for soldering inspection
    Publication number: 20040101190
    Abstract: A characteristic amount calculating device for soldering inspection. The characteristic amount calculating device includes a design information inputting section for inputting design information of an inspection object, an inspection standard inputting section for inputting an inspection standard, a solder shape calculating section for calculating shape information of a solder fillet according to the design information, and an inspection image calculating section for calculating an inspection image according to the shape information.
    Type: Application
    Filed: October 24, 2003
    Publication date: May 27, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Masatomo Maida, Shuzo Igarashi
  • Semiconductor device having a bump which is inspected from outside and a circuit board used with such a semiconductor device
    Patent number: 5828128
    Abstract: A BGA-type semiconductor device has a soldering bump a soldered state of which can be easily checked by visual inspection. A package has a bottom surface which faces the wiring board when the semiconductor device is mounted on the wiring board. A plurality of soldering bumps are provided on the bottom surface of the package. The soldering bumps are in a plurality of different sizes, and are located in positions where the soldering bumps are observable from outside of the package when the semiconductor device is mounted on the wiring board.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: October 27, 1998
    Assignee: Fujitsu, Ltd.
    Inventors: Yutaka Higashiguchi, Toshio Kumai, Yasuhiro Teshima, Mamoru Niishiro, Yasushi Kobayashi, Yukio Sekiya, Shuzo Igarashi, Yasuhiro Ichihara
  • Semiconductor device and semiconductor device mounting board
    Patent number: 5760469
    Abstract: A semiconductor device includes a package having opposing surfaces, a first terminal for an outer connection supported by said package and electronic components supported by said package, and the opposing surfaces of the package having slits so that a shape of the package can be changed in a mounted state. Therefore, stress applied to soldered junctions of the first and second terminals is decreased.
    Type: Grant
    Filed: February 16, 1996
    Date of Patent: June 2, 1998
    Assignee: Fujitsu Limited
    Inventors: Yutaka Higashiguchi, Mitsuo Inagaki, Toshio Kumai, Ryoichi Ochiai, Yasuhiro Teshima, Mamoru Niishiro, Yasushi Kobayashi, Hideaki Tamura, Hiroshi Iimura, Seishi Chiba, Yukio Sekiya, Shuzo Igarashi, Yasuhiro Ichihara