Patents by Inventor Shuzo Otsuka

Shuzo Otsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7827463
    Abstract: In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: November 2, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shuzo Otsuka, Kuninori Kawabata, Toshikazu Nakamura, Akira Kikutake
  • Patent number: 7548468
    Abstract: A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge operation after a refresh operation, and is retained at a second voltage higher than the first voltage during the precharge operation after an access operation. In the precharge operation after the refresh operation, therefore, the second voltage is not used so that the current consumption of the generating circuit of the second voltage is reduced. Thus, it is possible to reduce the current consumption (or the standby current) during the standby period for which the internal refresh requests continuously occur.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: June 16, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kuninori Kawabata, Shuzo Otsuka
  • Patent number: 7327627
    Abstract: Out of memory blocks arranged in one direction, the memory blocks arranged at both ends are included in a partial area. Since part of control circuits operating the memory blocks arranged at the both ends are not shared by the other memory blocks, switching circuits connecting these control circuits to the memory blocks are constantly settable to an ON state. Since ON/OFF control of the switching circuits is not necessary, power consumption required for accessing the memory blocks arranged at the both ends is smaller than that required for accessing the other memory blocks. Therefore, including the memory blocks arranged at the both ends in a partial area makes it possible to reduce power consumption during a partial refresh mode (standby current).
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: February 5, 2008
    Assignee: Fujitsu Limited
    Inventors: Kuninori Kawabata, Shuzo Otsuka
  • Publication number: 20060285405
    Abstract: A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge operation after a refresh operation, and is retained at a second voltage higher than the first voltage during the precharge operation after an access operation. In the precharge operation after the refresh operation, therefore, the second voltage is not used so that the current consumption of the generating circuit of the second voltage is reduced. Thus, it is possible to reduce the current consumption (or the standby current) during the standby period for which the internal refresh requests continuously occur.
    Type: Application
    Filed: August 24, 2006
    Publication date: December 21, 2006
    Inventors: Kuninori Kawabata, Shuzo Otsuka
  • Publication number: 20060239106
    Abstract: Out of memory blocks arranged in one direction, the memory blocks arranged at both ends are included in a partial area. Since part of control circuits operating the memory blocks arranged at the both ends are not shared by the other memory blocks, switching circuits connecting these control circuits to the memory blocks are constantly settable to an ON state. Since ON/OFF control of the switching circuits is not necessary, power consumption required for accessing the memory blocks arranged at the both ends is smaller than that required for accessing the other memory blocks. Therefore, including the memory blocks arranged at the both ends in a partial area makes it possible to reduce power consumption during a partial refresh mode (standby current).
    Type: Application
    Filed: June 14, 2006
    Publication date: October 26, 2006
    Inventors: Kuninori Kawabata, Shuzo Otsuka
  • Publication number: 20060236206
    Abstract: In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.
    Type: Application
    Filed: November 10, 2005
    Publication date: October 19, 2006
    Inventors: Shuzo Otsuka, Kuninori Kawabata, Toshikazu Nakamura, Akira Kikutake
  • Patent number: 7064589
    Abstract: A semiconductor device which is driven by a first potential, a second potential lower than the first potential, and a third potential lower than the second potential includes a first Pch transistor and a first Nch transistor connected in series between the first potential and the third potential, a second Pch transistor having a drain node thereof connected to a gate node of the first Nch transistor, and a second Nch transistor having a source node thereof connected to a source node of the second Pch transistor, wherein the drain node and gate node of the second Nch transistor are fixed to the second potential and the first potential, respectively.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: June 20, 2006
    Assignee: Fujitsu Limited
    Inventors: Toshimi Ikeda, Kuninori Kawabata, Shuzo Otsuka
  • Publication number: 20050152207
    Abstract: A semiconductor device which is driven by a first potential, a second potential lower than the first potential, and a third potential lower than the second potential includes a first Pch transistor and a first Nch transistor connected in series between the first potential and the third potential, a second Pch transistor having a drain node thereof connected to a gate node of the first Nch transistor, and a second Nch transistor having a source node thereof connected to a source node of the second Pch transistor, wherein the drain node and gate node of the second Nch transistor are fixed to the second potential and the first potential, respectively.
    Type: Application
    Filed: March 10, 2005
    Publication date: July 14, 2005
    Inventors: Toshimi Ikeda, Kuninori Kawabata, Shuzo Otsuka